CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
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Functional Description
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are
3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM
designed specifically to support unlimited true back-to-back
read/write operations with no wait state insertion. The
CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33
are
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133 MHz device).
Write operations are controlled by the two or four byte write
select (BW
X
) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
No Bus Latency (NoBL) architecture eliminates dead cycles
between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
❐
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133 MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in JEDEC-standard Pb-free 100-pin TQFP packages
Three chip enables for simple depth expansion
Automatic power-down feature available using ZZ mode or CE
deselect
Burst capability – linear or interleaved burst order
Low standby power
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
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Selection Guide
Description
Maximum access time
Maximum operating current
× 18
× 36
133 MHz
6.5
129
149
100 MHz
8.5
114
134
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-97852 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 8, 2018
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1371KV33
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Logic Block Diagram – CY7C1371KVE33
A0, A1, A
MODE
C
/CE
ADDRESS
REGISTER
A
1
A
0
ADV or /LD
C
D
1
D
0
Q
1
Q
0
A
1'
A
0'
BURST LOGIC
CLK
/CEN
WRITE ADDRESS
REGISTER
S
E
N
S
E
A
M
P
S
D
A
T
A
O
U
T
P
U
T
B
U
F
F
E
R
S
ADV or /LD
/BW
A
/BW
B
/BW
C
/BW
D
/WE
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
MEMORY
ARRAY
ECC
DECODER
S
T
E
E
R
I
N
G
DQ
S
DQP
A
DQP
B
DQP
C
DQP
D
E
/OE
/CE1
CE2
/CE1
READ
LOGIC
ECC
ENCODER
INPUT
REGISTER
E
ZZ
SLEEP
CONTROL
Document Number: 001-97852 Rev. *F
Page 2 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1373KV33
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
WE
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Document Number: 001-97852 Rev. *F
Page 3 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ................................................. 9
Burst Write Accesses .................................................. 9
Sleep Mode ............................................................... 10
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Partial Truth Table for Read/Write ................................ 12
Partial Truth Table for Read/Write ................................ 12
Maximum Ratings ........................................................... 13
Operating Range ............................................................. 13
Neutron Soft Error Immunity ......................................... 13
Electrical Characteristics ............................................... 13
Capacitance .................................................................... 15
Thermal Resistance ........................................................ 15
AC Test Loads and Waveforms ..................................... 15
Switching Characteristics .............................................. 16
Switching Waveforms .................................................... 17
Ordering Information ...................................................... 20
Ordering Code Definitions ......................................... 20
Package Diagrams .......................................................... 21
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 001-97852 Rev. *F
Page 4 of 24
CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
CY7C1371KV33/CY7C1371KVE33
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
ADV/LD
WE
OE
A
82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
81
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
A1
A0
V
SS
MODE
V
DD
A
A
A
A
A
A
A
NC/144M
NC/288M
NC/72M
Document Number: 001-97852 Rev. *F
NC/36M
A
A
A
A
Page 5 of 24
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