DATASHEET
ISL70002SEH
Radiation Hardened and SEE Hardened 18A Synchronous Buck Regulator with
Current Sharing
The
ISL70002SEH
is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a
tightly regulated output voltage that is externally adjustable
from 0.8V to ~85% of the input voltage. Output load current
capability is primarily determined by PVIN voltage with up to
22A for a single IC at PVIN
≤
5.5V for T
J
≤
+125°C. Two
ISL70002SEH devices configured to current share can
provide up to 38A of total output current at PVIN
≤
5.5V for
T
J
≤
+125°C assuming ±27% worst-case current share
accuracy.
Refer to the Features section for maximum output current
detailed constraints and recommendations.
The ISL70002SEH uses peak current-mode control with
integrated error amp compensation and pin selectable slope
compensation. Switching frequency is also pin selectable to
either 1MHz or 500kHz. Two devices can be synchronized
180° out-of-phase to reduce input RMS ripple current.
High integration makes the ISL70002SEH an ideal choice to
power small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like Field Programmable Gate Arrays
(FPGAs) that require separate core and I/O voltages.
FN8264
Rev 9.00
May 31, 2018
Features
• DLA SMD
5962-12202
• Maximum Output current for a single device:
- PVIN
≤
5.5V; 18A to 22A at T
J
= 125
°
C with Schottky
Clamp Diode LX to GND
- PVIN
≤
5.5V; up to 18A at T
J
= 125
°
C without Schottky
Clamp Diode
- PVIN
≤
6.2V; up to 14A at T
J
= 125
°
C, 12A at T
J
= 150
°
C
without Schottky Clamp Diode
• Maximum Output current for two current sharing devices
based on 27% worst case current share mismatch:
- PVIN
≤
5.5V; 28A to 38A at T
J
= 125
°
C with Schottky
Clamp Diode LX to GND
- PVIN
≤
5.5V; up to 28A at T
J
= 125
°
C without Schottky
Clamp Diode
- PVIN
≤6.2V;
up to 22A at T
J
= 125
°
C, 19A at 150
°
C
without Schottky Clamp Diode
• Available in a thermally enhanced heat spreader package
(R64.C)
• 1MHz or 500kHz switching frequency
• 3V to 5.5V supply voltage range
• ±1% reference voltage (line, load, temperature, and rad)
• Prebiased load compatible
• Redundancy/junction isolation: exceptional SET
performance
• Excellent transient response
• High efficiency >90%
• Two ISL70002SEH synchronization, inverted-phase
• Comparator input for enable and power-good
• Input undervoltage, output undervoltage, and adjustable
output overcurrent protection
• QML qualified per MIL-PRF-38535
• Full military temperature range operation (-55
°
C to +125
°
C)
• Radiation environment
- High dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)*
*Level guaranteed by characterization; “EH” version is
production tested to 50krad(Si).
• SEE hardness
- SEL and SEB LET
TH
. . . . . . . . . . . . . . . . 86.4MeV/mg/cm
2
- SEFI LET
TH
. . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm
2
- SET LET
TH
. . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm
2
Applications
• FPGA, CPLD, DSP, CPU core, and I/O voltages
• Low-voltage, high-density distributed power systems
Related Literature
For a full list of related documents, visit our website
•
ISL70002SEH
product page
FN8264 Rev 9.00
May 31, 2018
Page 1 of 27
ISL70002SEH
100
95
25
20
AMPLITUDE (V)
15
CH2 SLAVE LX + 15V
CH1 MASTER LX + 20V
90
EFFICIENCY (%)
85
80
75
70
10
CH3 VOUT x 10
65
60
0.95VOUT
1.8VOUT
1.2VOUT
2.5VOUT
1.5VOUT
3.3VOUT
5
CH4 SYNC
55
50
0
2
4
6
8
10
12
14
16
18
20
22
0
-6
-4
-2
0
2
4
6
8
10
12
14
LOAD CURRENT (A)
FIGURE 1. EFFICIENCY 5V INPUT, 500kHz, T
case
= +25°C
FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm
2
FN8264 Rev 9.00
May 31, 2018
Page 2 of 27
ISL70002SEH
Functional Block Diagram
ISHREFA
ISHREFB
ISHREFC
ISHA
ISHB
ISHC
AVDD
DVDD
EN
PORSEL
SC0
SC1
POWER-ON
RESET (POR)
CURRENT
SHARE
ISHEN
ISHSL
ISHCOM
PVINx
CURRENT
SENSE
SS
SOFT-
START
SLOPE
COMPENSATION
PWM
CONTROL
LOGIC
FB
EA
GM
GATE
DRIVE
LXx
COMPENSATION
GND
PGNDx
OCA
OCB
OCSSA
OCSSB
PGOOD
UV
POWER-GOOD
OVERCURRENT
ADJUST
REF
PWM
REFERENCE
0.6V
BIT
TDI
TDO
FSEL
SYNC
M/S
PGNDx
PGNDx
TRIM
TPGM
AGND
DGND
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8264 Rev 9.00
May 31, 2018
Page 3 of 27
ISL70002SEH
Ordering Information
ORDERING SMD NUMBER
(Note
2)
5962R1220201VXC
5962R1220201VYC
5962R1220201V9A
N/A
N/A
N/A
N/A
N/A
N/A
NOTES:
1. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
3. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for
engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA
SMD and are in the same form and fit as the qualified device. The /SAMPLE die is capable of meeting the electrical limits and conditions specified
in the DLA SMD at +25°C only. The /SAMPLE is a die and does not receive 100% screening across the temperature range to the DLA SMD electrical
limits. These part types do not come with a certificate of conformance because there is no radiation assurance testing and they are not DLA qualified
devices.
4. Evaluation board uses the /PROTO parts. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE)
immunity.
PART NUMBER
(Note
1)
ISL70002SEHVF
ISL70002SEHVFE
ISL70002SEHVX
ISL70002SEHF/PROTO (Notes
3)
ISL70002SEHFE/PROTO (Notes
3)
ISL70002SEHX/SAMPLE (Notes
3)
ISL70002SEHEVAL1Z (Note
4)
ISL70002SEHEVAL2Z (Note
4)
ISL70002SEHDEMO1Z (Note
4)
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS Compliant)
64 Ld CQFP
Die
64 Ld CQFP
Die
Evaluation Board
Current Sharing Evaluation Board
High Current Sharing Demonstration Board
R64.A
64 Ld CQFP with heat spreader R64.C
PKG.
DWG. #
R64.A
64 Ld CQFP with heat spreader R64.C
Pin Configuration
(64 LD CQFP)
TOP VIEW
OCSSA
OCSSB
PGND1
PGND2
PVIN2
PVIN1
OCA
OCB
REF
LX1
LX2
EN
FOR PIN 1 LOCATION
PVIN3
BOTTOM SIDE DETAIL
NC/HS*
SC1
SC0
1 (FB)
FB
ISHA
ISHREFA
ISHB
ISHREFB
ISHC
ISHREFC
AVDD
AGND
DGND
DVDD
SS
PGOOD
ISHCOM
ISHSL
ISHEN
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
LX3
PGND3
PGND4
LX4
PVIN4
PVIN5
LX5
PGND5
PGND6
LX6
PVIN6
PVIN7
LX7
PGND7
PGND8
LX8
PRODUCT BRAND
NAME AREA
(
Note 5
)
10
11
12
13
14
15
*HEAT SPREADER OUTLINE
35
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTE:
5. The ESD triangular mark is indicative of Pin
#1’s location. It is a part of the device
marking and is placed on the lid in the
quadrant where Pin #1 is located.
FSEL
SYNC
LX10
PGND9
LX9
PVIN9
NC
PVIN10
PGND10
PORSEL
TPGM
* Indicates heat spreader package R64.C
FN8264 Rev 9.00
May 31, 2018
PVIN8
GND
TDO
M/S
TDI
Page 4 of 27
ISL70002SEH
Pin Descriptions
R64.A
R64.C
PIN NUMBER PIN NUMBER PIN NAME
1
FB
DESCRIPTION
Voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and from FB to AGND
to adjust the output voltage in accordance with
Equation 1:
V
OUT
=
V
REF
1
+
R
T
R
B
(EQ. 1)
where:
V
OUT
= output voltage
V
REF
= reference voltage (0.6V typical)
R
T
= top divider resistor (Must be 1kΩ
R
B
= bottom divider resistor
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across R
T
to mitigate
SEE and to improve stability margins.
If using current share, tie FB of the master to FB of the slave.
2, 4, 6
ISHA,
If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), these pins are outputs that provide a
ISHB, ISHC current equal to 25 times the redundant A/B/C error amp output currents plus ISHREFA/ISHREFB/ISHREFC
(nominally 100µA each). If configured as a current share slave (ISHSL = DVDD, ISHEN = DVDD), the
ISHA/ISHB/ISHC pins are inputs that become the slave’s redundant A/B/C error amp output current. If using
current share, tie ISHA/ISHB/ISHC of the master to ISHA/ISHB/ISHC of the slave. If not using current share,
tie ISHA/ISHB/ISHC to DVDD. ISHA/ISHB/ISHC are tri-stated prior to a valid POR and when ISHEN = DGND.
ISHREFA, If configured as a current share master (ISHSL = DGND, ISHEN = DVDD), these pins provide a reference output
ISHREFB, current equal to 100µA each. If configured as a current share slave (ISHSL = DVDD, ISHEN = DVDD), the
ISHREFC ISHREFA/ISHREFB/ISHREFC pins accept a reference input current. For a current share slave, this input current
is used together with the ISHA/ISHB/ISHC current to determine the master’s redundant A/B/C error amp
output current. If using current share, tie ISHREFA/ISHREFB/ISHREFC of the MASTER to
ISHREFA/ISHREFB/ISHREFC of the slave. If not using current share, tie ISHREFA/ISHREFB/
ISHREFC to DVDD. The purpose of the reference current is to reduce the impact of external noise coupling onto
ISHA/ISHB/ISHC. ISHREFA/ISHREFB/ISHREFC are tri-stated prior to a valid POR and when ISHEN = DGND.
AVDD
Bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω resistor and
a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. AVDD should be the
same voltage as DVDD and PVINx (±200mV).
Analog ground associated with the internal analog control circuitry. Connect this pin directly to the PCB ground
plane.
Digital ground associated with the internal digital control circuitry. Connect this pin directly to the PCB ground
plane.
Bias supply input to the internal digital control circuitry. Locally filter this pin to DGND using a 1Ω resistor and
a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC. DVDD should be the
same voltage as AVDD and PVINx (±200mV).
Soft-start input. Connect a ceramic capacitor from this pin to DGND to set the soft-start output ramp time in
accordance with
Equation 2:
t
SS
=
C
SS
V
REF
I
SS
(EQ. 2)
3, 5, 7
8
9
10
11
AGND
DGND
DVDD
12
SS
where:
t
SS
= soft-start output ramp time
C
SS
= soft-start capacitor
V
REF
= reference voltage (0.6V typical)
I
SS
= soft-start charging current (23µA typical)
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
If using current share, C
SS
of the slave should be at least twice the C
SS
of the master.
13
PGOOD
Power-good output. This pin is an open drain logic output that is pulled to DGND when the output voltage is
outside a ±11% typical regulation window. This pin can be pulled up to any voltage from 0V to 5.5V,
independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is recommended. Bypass this pin
to DGND with a 10nF ceramic capacitor to mitigate SEE. If using current share, tie PGOOD of the master to
PGOOD of the slave.
FN8264 Rev 9.00
May 31, 2018
Page 5 of 27
Embedded System
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