DATASHEET
ISL85012
12A, 3.8V to 18V Input, Synchronous Buck Regulator
The
ISL85012
is a highly efficient, monolithic, synchronous
buck regulator that can deliver 12A of continuous output
current from a 3.8V to 18V input supply. The device uses
current mode control architecture with a fast transient
response and excellent loop stability.
The ISL85012 integrates very low ON-resistance high-side and
low-side FETs to maximize efficiency and minimize external
component count. The minimum BOM and easy layout
footprint are extremely friendly to space constraint systems.
The operation frequency of this device can be set using the
FREQ pin: 600kHz (FREQ = float) and 300kHz (FREQ = GND).
The device can also be synchronized to an external clock up to
1MHz.
Both high-side and low-side MOSFET current limit along with
reverse current limit, fully protects the regulator in an
overcurrent event. Selectable OCP schemes can fit various
applications. Other protections, such as input/output
overvoltage and over-temperature, are also integrated into the
device which give required system level safety in the event of
fault conditions.
The ISL85012 is offered in a space saving 15 Ld 3.5mmx3.5mm
Pb-free TQFN package with great thermal performance and
0.8mm maximum height.
FN8677
Rev.2.00
Mar 17, 2017
Features
• Power input voltage range variable 3.8V to 18V
• PWM output voltage adjustable from 0.6V
• Up to 12A output load
• Prebias start-up, fixed 3ms soft-start
• Selectable f
SW
of 300kHz, 600kHz, and external
synchronization up to 1MHz
• Peak current mode control
- DCM/CCM
- Thermally compensated current limit
- Internal/external compensation
• Open-drain, PG window comparator
• Output overvoltage and thermal protection
• Input overvoltage protection
• Integrated boot diode with undervoltage detection
• Selectable OCP schemes
- Hiccup OCP
- Latch-off
• Compact size 3.5mmx3.5mm
Related Literature
• For a full list of related documents please visit our web page
-
ISL85012
product page
Applications
• Servers and cloud infrastructure POLs
• IPCs, factory automation, PLCs
• Telecom and networking systems
• Storage systems
• Test measurement
C
5
1µF
R
2
R
3
200
15
VIN
14
EN
13
DNC
12
DNC
11
COMP
9
10
FB
100k
R
1
200k
C
1
4.7pF
VIN
PVIN
L1
0.68µH
4.5-18V
3x22µF
C
in
PHASE
8
V
OUT
GND
GND
SYNC MODE FREQ
1
2
3
PG
4
7
VDD BOOT
5
6
C
4
100nF
C
OUT
3x100µF
CERAMIC
1.8V/12A
GND
C
3
2.2µF
FIGURE 1. TYPICAL APPLICATION SCHEMATIC FOR INTERNAL COMPENSATION
FN8677 Rev.2.00
Mar 17, 2017
Page 1 of 19
ISL85012
Typical Application Schematic
C
5
1µ F
80 .6 k
R
3
330 pF
C
2
R
1
20k
C
1
47pF
15
VIN
VIN
14
EN
13
DNC
12
DNC
11
C O MP
9
10
FB
R
2
10k
L1
0 .68µ H
4 .5-18 V
3x22 µ F
C
in
PH A SE
PH A SE
8
8
V
OUT
PVIN
PVIN
GND
GND
GND
SYN C MO D E FR EQ
1
2
3
PG
4
7
7
VD D
5
BOOT
6
C
4
100 nF
C
OUT
3x 100 µ F
C ER A MIC
1.8 V/12A
GND
C
3
2 .2µ F
FIGURE 2. TYPICAL APPLICATION SCHEMATIC FOR EXTERNAL COMPENSATION
TABLE 1. DESIGN TABLE FOR DIFFERENT OUTPUT VOLTAGE
V
OUT
(V)
V
IN
(V)
FREQ (kHz)
Compensation
C
in
(µF)
C
out
(µF)
L
1
(µH)
R
1
(kΩ)
R
2
(kΩ)
C
1
(pF)
NOTES:
1. The design table is referencing the schematic shown in
Figure 1.
2. Ceramic capacitors are selected for 22µF and 100µF in the table.
3. 560µF (14mΩ) and 330µF (10mΩ) are selected low ESR conductive polymer aluminum solid capacitors.
4. Inductor 7443340068 (0.68µH), 7443340100 (1µH) and 7443340150 (1.5µH) from Wurth Electronics are selected for the above applications.
5. Recommend to keep the inductor peak-to-peak current less than 5A.
0.9
4.5 to 18
300
Internal
3x22
0.68
100
200
DNP
1
4.5 to 18
300
Internal
3x22
0.68
100
150
DNP
1.2
4.5 to 18
300
Internal
3x22
1
147
147
DNP
1.5
4.5 to 18
600
Internal
3x22
4x100
0.68
150
100
10
1.8
4.5 to 18
600
Internal
3x22
3x100
0.68
200
100
4.7
2.5
4.5 to 18
600
Internal
3x22
4x47
1
301
95.3
4.7
3.3
4.5 to 18
600
Internal
3x22
4x47
1
365
80.6
3.3
5
6 to 18
600
Internal
3x22
4x47
1.5
365
49.9
3.3
2x560 + 4x100 2x330 + 3x100 2x330 + 3x100
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
ISL85003
ISL85003A
ISL85005
ISL85005A
ISL85012
INTERNAL/EXTERNAL
COMPENSATION
Yes
Yes
Yes
Yes
Yes
EXTERNAL FREQUENCY
SYNC
Yes
No
Yes
No
Yes
PROGRAMMABLE
SOFT-START
No
Yes
No
Yes
No
SWITCHING
FREQUENCY (kHz)
500
500
500
500
300 or 600 selectable
CURRENT
RATING (A)
3
3
5
5
12
FN8677 Rev.2.00
Mar 17, 2017
Page 2 of 19
ISL85012
Ordering Information
PART NUMBER
(Notes
6, 7, 8)
ISL85012FRZ-T
ISL85012FRZ-T7A
ISL85012EVAL1Z
NOTES:
6. Refer to
TB347
for details on reel specifications.
7. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
8. For Moisture Sensitivity Level (MSL), see product information page for
ISL85012.
For more information on MSL, see tech brief
TB363.
PART MARKING
5012
5012
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
-40 to +125
TAPE AND REEL
(UNITS)
6k
250
PACKAGE
(RoHS COMPLIANT)
15 Ld 3.5mmx3.5mm TQFN
15 Ld 3.5mmx3.5mm TQFN
PKG.
DWG. #
L15.3.5x3.5
L15.3.5x3.5
Functional Block Diagram
PG
NC
FREQ
SYNC
EN
VDD
DELAY
POR
MODE
OVP
THERMAL
SHUT
DOWN
POWER-ON RESET MONITOR
LDO
VIN
OSCILLATOR
UVP
PVIN
CSA
FAULT
MONITOR
CIRCUITS
HIGH SIDE
OCP
SCHEME
SETTING
20V
BOOT
BOOT
UVP
NC
INTERNAL SS
0.6V
REF
FB
FREQ
800/1200 k
30pF
EA
GATE DRIVER
CONTROL LOGIC
PHASE
VDD
SLOPE
COMP
CSA
ZERO CROSS
DETECTOR
NEGATIVE
CURRENT LIMIT
AND FORWARD
CURRENT LIMIT
GND
DCM
COMP
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8677 Rev.2.00
Mar 17, 2017
Page 3 of 19
ISL85012
Pin Configuration
ISL85012
(15 LD 3.5mmx3.5mm TQFN)
TOP VIEW
15
VIN
14
EN
13
DNC
12
DNC
11
COMP
9
10
FB
PVIN
PVIN
PHASE
PHASE
8
8
GND
GND
SYNC MODE FREQ
1
2
3
PG
4
7
7
VDD BOOT
5
6
Pin Descriptions
PIN#
1
2
3
4
5
PIN
NAME
SYNC
MODE
FREQ
PG
VDD
DESCRIPTION
Synchronization and mode selection pin. Connect to VDD or float for PWM mode. Connect to GND for DCM mode in the light-load
condition. Connect to an external clock signal for synchronization with the rising edge trigger.
OCP scheme select pin. Short it to GND for latch-off mode. Float it for hiccup mode.
Default frequency selection pin. Short it to GND for 300kHz. Float it for 600kHz.
Power-good, open-drain output. It requires a pull-up resistor (10kΩ to 100kΩ) between PG and VDD or a voltage not exceeding
5.5V. PG pulls high when FB is in the range of ~90% to ~116% of its intended value.
Low dropout linear regulator decoupling pin. The VDD is the internally generated 5V supply voltage and is derived from VIN. The
VDD is used to power all the internal core analog control blocks and drivers. Connect a 2.2µF capacitor from VDD to the board
ground plane. If the V
IN
is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency.
BOOT is the floating bootstrap supply pin for the high-side power MOSFET gate driver. A bootstrap capacitor, usually 0.1µF, is
required from BOOT to PHASE.
Reference of the power circuit. For thermal relief, this pin should be connected to the ground plane by vias.
Switch node connection to the internal power MOSFETs (source of upper FET and drain of lower FET) and the external output
inductor.
Input supply for the PWM regulator power stage. A decoupling capacitor, typically ceramic, is required to be connected between
this pin and GND.
Inverting input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB.
Output of the error amplifier. Compensation network between COMP and FB to configure external compensation. Place a 200Ω
resistor between COMP and GND for internal compensation, which is used to meet most applications.
Do Not Connect to pin. Float the pins in the design.
Enable input. The regulator is held off when this pin is pulled to ground. The device is enabled when the voltage on this pin rises
to about 0.6V.
Input supply for the control circuit and the source for the internal linear regulator that provides bias for the IC.
A decoupling capacitor, typically 1µF ceramic, is required connected between VIN and GND.
6
7
8
9
10
11
12, 13
14
15
BOOT
GND
PHASE
PVIN
FB
COMP
DNC
EN
VIN
FN8677 Rev.2.00
Mar 17, 2017
Page 4 of 19
ISL85012
Absolute Maximum Ratings
VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PVIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns)
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
VDD, COMP, SYNC, PG, FB, MODE, FREQ, SS, IOCP to GND . . . -0.3V to +7V
ESD Rating
Human Body Model (Tested per JS-001-2014) . . . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD78E; Class 2, Level A, +125°C) . . . . . . . 100mA
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
TQFN Package (Notes
9, 10)
. . . . . . . . . . . .
33
1.2
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB49
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V
PVIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V to 18V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 12A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
9.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features, except with
3 vias under the GND EPAD strip contacting the GND plane, and two vias under the VIN EPAD strip contacting the VIN plane. See Tech Brief
TB379.
10. For
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: T
J
= -40°C to +125°C, V
IN
= 4.5V to 18V, unless otherwise noted. Typical values are at
T
A
= +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
SUPPLY VOLTAGE
PVIN Voltage Range
V
IN
Voltage Range
V
IN
Quiescent Supply Current
V
IN
Shutdown Supply Current
POWER-ON RESET
PVIN POR Threshold
V
IN
POR Threshold
EN POR Threshold
V
DD
POR Threshold
INTERNAL VDD LDO
V
DD
Output Voltage Regulation Range
V
DD
Output Current Limit
LDO Dropout Voltage
OSCILLATOR
Nominal Switching Frequency
Nominal Switching Frequency
Minimum On-Time
Minimum Off-Time
Synchronization Range
SYNC Logic Input Low
SYNC Logic Input High
1.2
f
SW1
f
SW2
t
ON
t
OFF
100
FREQ = float
FREQ = GND
I
OUT
= 0mA
540
250
600
280
90
140
660
310
150
170
1000
0.5
kHz
kHz
ns
ns
kHz
V
V
V
IN
= 5V, I
VDD
= 30mA
V
IN
= 6V to 18V, I
VDD
= 0mA to 30mA
4.3
5.0
80
0.65
5.5
V
mA
V
Rising edge
Falling edge
Rising edge
Falling edge
Rising edge
Hysteresis
Rising edge
Falling edge
2.4
3.4
0.5
0.6
100
3.6
0.7
1.9
4.49
2.9
V
V
V
V
V
mV
V
V
PVIN
VIN
Electrical Specifications
SYMBOL
TEST CONDITIONS
MIN
(Note
11)
3.8
4.5
TYP
MAX
(Note
11)
18
18
UNIT
V
V
mA
µA
I
Q
I
SD
EN = 2V, FB = 0.64V
EN = GND
3
8
5
13
FN8677 Rev.2.00
Mar 17, 2017
Page 5 of 19
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