Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C T
JUNCTION
MEMORY
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
PERIPHERALS FEATURES
See
Figure 1,
Processor Block Diagram and
Table 1,
Processor
Comparison
SYSTEM CONTROL BLOCKS
PERIPHERALS
1× TWI
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
CONTROL
WATCHDOG
8× TIMER
1× COUNTER
L2 MEMORY
2× CAN
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
B
UP TO
1M BYTE SRAM
512K BYTE
ROM
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
2× UART
SPI HOST PORT
2x QUAD SPI
1x DUAL SPI
GPIO
2× SPORT
SYSTEM FABRIC
1× MSI
(SD/SDIO)
EXTERNAL
BUS
INTERFACES
MEMORY
PROTECTION
OTP
MEMORY
HARDWARE
FUNCTIONS
SYSTEM PROTECTION
ANALOG
SUB
SYSTEM
1× PPI
STATIC MEMORY
CONTROLLER
3× MDMA
STREAMS
2× CRC
CRYPTO ENGINE (SECURITY)
DYNAMIC MEMORY
CONTROLLER
HADC
1× RTC
LPDDR
DDR2
16
1× USB 2.0 HS OTG
Figure 1. Processor Block Diagram
Blackfin, Blackfin+, and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. C
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ADSP-BF700/701/702/703/704/705/706/707
TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Peripherals Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Blackfin+ Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Processor Infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Security Features Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Processor Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Processor Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power and Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
System Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Related Signal Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ADSP-BF70x Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . 17
184-Ball CSP_BGA Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . 21
GPIO Multiplexing for 184-Ball CSP_BGA . . . . . . . . . . . . . . . . . . 28
12 mm × 12 mm 88-Lead LFCSP (QFN) Signal
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPIO Multiplexing for 12 mm × 12 mm 88-Lead
LFCSP (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADSP-BF70x Designer Quick Reference . . . . . . . . . . . . . . . . . . . . . . 37
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
HADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ADSP-BF70x 184-Ball CSP_BGA Ball Assignments
(Numerical by Ball Number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN)
Lead Assignments (Numerical by Lead Number) . . . . . . 109
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Surface-Mount Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Automotive Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
REVISION HISTORY
3/2018—Rev. B to Rev. C
Change to
OTP Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Figure 3,
ADSP-BF706/ADSP-BF707 Inter-
nal/External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Moved
Security Features Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Change to
Housekeeping ADC (HADC) . . . . . . . . . . . . . . . . . . . . . . 12
Change to JTG_SWCLK Direction, Table 6 in
ADSP-BF70x
Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Changes to
Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . 98
Changes to
USB Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Rev. C
| Page 2 of 116
| March 2018
ADSP-BF700/701/702/703/704/705/706/707
GENERAL DESCRIPTION
The ADSP-BF70x processor is a member of the Blackfin
®
family of products. The Blackfin processor combines a dual-
MAC 16-bit state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set architec-
ture. New enhancements to the Blackfin+ core add 32-bit MAC
and 16-bit complex MAC support, cache enhancements, branch
prediction and other instruction set improvements—all while
maintaining instruction set compatibility to previous Blackfin
products.
The processor offers performance up to 400 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
By integrating a rich set of industry-leading system peripherals
and memory (shown in
Table 1),
the Blackfin processor is the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation, video/image analysis,
biometric and power/motor control applications.
Table 1. Processor Comparison
Processor Feature
Maximum Speed Grade (MHz)
1
Maximum SYSCLK (MHz)
Package Options
GPIOs
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad (L1 Data C)
L2 SRAM
L2 ROM
DDR2/LPDDR (16-bit)
2
IC
Up/Down/Rotary Counter
GP Timer
Watchdog Timer
GP Counter
SPORTs
Quad SPI
Dual SPI
SPI Host Port
USB 2.0 HS OTG
Parallel Peripheral Interface
CAN
UART
Real-Time Clock
Static Memory Controller (SMC)
Security Crypto Engine
SD/SDIO (MSI)
4-Channel 12-Bit ADC
Memory (bytes)
1
ADSP-
BF700
200
100
88-Lead
LFCSP
43
ADSP-
BF701
ADSP-
BF702
ADSP-
BF703
ADSP-
BF704
400
200
ADSP-
BF705
ADSP-
BF706
ADSP-
BF707
184-Ball
CSP_BGA
47
88-Lead
LFCSP
43
128K
No
Yes
4-bit
No
8-bit
Yes
184-Ball
88-Lead
184-Ball
CSP_BGA
LFCSP
CSP_BGA
47
43
47
48K
16K
32K
32K
8K
256K
512K
512K
No
Yes
No
Yes
1
1
8
1
1
2
2
1
1
1
1
2
2
1
Yes
Yes
4-bit
8-bit
4-bit
8-bit
No
Yes
No
Yes
88-Lead
LFCSP
43
184-Ball
CSP_BGA
47
1024K
No
Yes
4-bit
No
8-bit
Yes
Other speed grades available.
Rev. C
| Page 3 of 116
| March 2018
ADSP-BF700/701/702/703/704/705/706/707
BLACKFIN+ PROCESSOR CORE
As shown in
Figure 1,
the processor integrates a Blackfin+
processor core. The core, shown in
Figure 2,
contains two 16-bit
multipliers, one 32-bit multiplier, two 40-bit accumulators
(which may be used together as a 72-bit accumulator), two
40-bit ALUs, one 72-bit ALU, four video ALUs, and a 40-bit
shifter. The computation units process 8-, 16-, or 32-bit data
from the register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
The core can perform two 16-bit by 16-bit multiply-accumu-
lates or one 32-bit multiply-accumulate in each cycle. Signed
and unsigned formats, rounding, saturation, and complex mul-
tiplies are supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, divide primitives, saturation and rounding, and
sign/exponent detection. The set of video instructions include
byte alignment and packing operations, 16-bit and 8-bit adds
with clipping, 8-bit average operations, and 8-bit subtract/abso-
lute value/accumulate (SAA) operations. Also provided are the
compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If a second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1 32
DA0 32
TO MEMORY
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD 32
LD1 32
LD0 32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
32
32
ASTAT
SEQUENCER
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
40
BARREL
SHIFTER
72
40
A0
32
DATA ARITHMETIC UNIT
A1
32
40
CONTROL
UNIT
40
8
16
8
32
8
16
8
DECODE
LOOP BUFFER
ALIGN
Figure 2. Blackfin+ Processor Core
Rev. C
| Page 4 of 116
| March 2018
ADSP-BF700/701/702/703/704/705/706/707
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with dynamic branch prediction),
and subroutine calls. Hardware supports zero-overhead loop-
ing. The architecture is fully interlocked, meaning that the
programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor supports a modified Harvard architec-
ture in combination with a hierarchical memory structure. Level
1 (L1) memories are those that typically operate at the full pro-
cessor speed with little or no latency. At the L1 level, the
instruction memory holds instructions only. The data memory
holds data, and a dedicated scratchpad data memory stores
stack and local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• Control of all asynchronous and synchronous events to the
processor is handled by two subsystems: the core event
controller (CEC) and the system event controller (SEC).
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
PROCESSOR INFRASTRUCTURE
The following sections provide information on the primary
infrastructure components of the ADSP-BF70x processor.
DMA Controllers
The processor uses direct memory access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processor can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each memory-to-
memory DMA stream uses two channels, where one channel is
the source channel, and the second is the destination channel.
All DMAs can transport data to and from all on-chip and off-
chip memories. Programs can use two types of DMA transfers,
descriptor-based or register-based. Register-based DMA allows
the processor to directly program DMA control registers to ini-
tiate a DMA transfer. On completion, the control registers may
be automatically updated with their original setup values for
continuous transfer. Descriptor-based DMA transfers require a
set of parameters stored within memory to initiate a DMA
sequence. Descriptor-based DMA transfers allow multiple
DMA sequences to be chained together and a DMA channel can
be programmed to automatically set up and start another DMA
transfer after the current sequence completes.
The DMA controller supports the following DMA operations.
• A single linear buffer that stops on completion.
• A linear buffer with negative, positive, or zero stride length.
• A circular, auto-refreshing buffer that interrupts when each
buffer becomes full.
INSTRUCTION SET DESCRIPTION
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. The Blackfin proces-
sor supports a limited multi-issue capability, where a 32-bit
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
Rev. C
| Page 5 of 116
| March 2018
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