RQA0009TXDQS
Silicon N-Channel MOS FET
REJ03G1520-0100
Rev.1.00
Jul 04, 2007
Features
•
High Output Power, High Gain, High Efficiency
Pout = +37.8 dBm, Linear Gain = 18 dB, PAE = 65%
(V
DS
= 6 V, f = 520 MHz)
•
Compact package capable of surface mounting
•
Electrostatic Discharge Immunity Test
(IEC Standard, 61000-4-2, Level4)
Outline
RENESAS Package code: PLZZ0004CA-A
(Package Name : UPAK
R
)
3
3
2
1
1
4
1. Gate
2. Source
3. Drain
4. Source
2, 4
Note:
Marking is “TX”.
*UPAK is a trademark of Renesas Technology Corp.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate to source voltage
Drain current
Channel dissipation
Channel temperature
Storage temperature
Note: Value at Tc = 25°C
Symbol
V
DSS
V
GSS
I
D
Pch
note
Tch
Tstg
Ratings
16
±5
3.2
15
150
–55 to +150
Unit
V
V
A
W
°C
°C
This device is sensitive to electro static discharge. An adequate careful handling procedure is requested.
REJ03G1520-0100 Rev.1.00 Jul 04, 2007
Page 1 of 12
RQA0009TXDQS
Electrical Characteristics
(Ta = 25°C)
Item
Zero gate voltage drain current
Gate to source leak current
Gate to source cutoff voltage
Forward Transfer Admittance
Input capacitance
Output capacitance
Reverse transfer capacitance
Output Power
Power Added Efficiency
Output Power
Power Added Efficiency
Symbol
I
DSS
I
GSS
V
GS(off)
|yfs|
Ciss
Coss
Crss
Pout
PAE
Pout
PAE
Min.
—
—
0.15
2.2
—
—
—
36.8
4.8
60
—
—
—
Typ
—
—
0.5
3.2
76
40
3.5
37.8
6.0
65
35.2
3.3
60
Max.
15
±2
0.8
4.4
—
—
—
—
—
—
—
—
—
Unit
µA
µA
V
S
pF
pF
pF
dBm
W
%
dBm
W
%
Test Conditions
V
DS
= 16 V, V
GS
= 0
V
GS
= ±5 V, V
DS
= 0
V
DS
= 6 V, I
D
= 1 mA
V
DS
= 6 V, I
D
= 1.6 A
V
GS
= 5 V, V
DS
= 0, f = 1 MHz
V
DS
= 6 V, V
GS
= 0, f = 1 MHz
V
DG
= 6 V, V
GS
= 0, f = 1 MHz
V
DS
= 6 V, I
DQ
= 180 mA
f = 520 MHz,
Pin = +25 dBm (316 mW)
V
DS
= 4.8 V, I
DQ
= 300 mA
f = 465 MHz,
Pin = +17 dBm (50 mW)
Main Characteristics
Maximum Channel Power
Dissipation Curve
Typical Output Characteristics
4
2.0 V
15
Pulse Test
1.75 V
Channel Power Dissipation Pch (W)
20
Drain Current I
D
(A)
3
1.5 V
2
1.25 V
1
10
5
V
GS
= 1.0 V
0
0
50
100
150
200
0
0
2
4
6
8
10
Case Temperature T
C
(°C)
Drain to Source Voltage V
DS
(V)
Forward Transfer Admittance
vs. Drain Current
Typical Transfer Characterisitics
Drain Current I
D
(A)
Forward Transfer Admittance |yfs| (S)
4
V
DS
= 6 V
Pulse Test
3
|yfs|
Forward Transfer Admittance |yfs| (S)
10.0
V
DS
= 6 V
Pulse Test
2
I
D
1.0
1
0
0
0.5
1.0
1.5
2.0
0.1
0.1
1.0
10.0
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
REJ03G1520-0100 Rev.1.00 Jul 04, 2007
Page 2 of 12
RQA0009TXDQS
Input Capacitance vs.
Gate to Source Voltage
90
1000
Output Capacitance vs.
Drain to Source Voltage
Output Capacitance Coss (pF)
Input Capacitance Ciss (pF)
80
70
100
60
50
V
DS
= 0
f = 1 MHz
40
-5 -4 -3 -2 -1
0
1
2
3
4
5
V
GS
= 0
f = 1 MHz
10
0.1
1
10
Gate to Source Voltage V
GS
(V)
Reverse Transfer Capacitance vs.
Drain to Gate Voltage
100
V
GS
= 0
f = 1 MHz
Drain to Source Voltage V
DS
(V)
Reverse Transfer Capacitance Crss (pF)
MSG, MAG vs. Frequency
Maximum Stable Gain MSG (dB)
Maximum Available Gain MAG (dB)
30
25
MSG
20
15
MAG
10
5
0
0
500
1000
1500
2000
V
DS
= 6 V
I
D
= 180 mA
10
1
0.1
1
10
Drain to Gate Voltage V
DG
(V)
Frequency f (MHz)
REJ03G1520-0100 Rev.1.00 Jul 04, 2007
Page 3 of 12
RQA0009TXDQS
Evaluation Circuit (f = 520 MHz)
C6
VG
R2
C4
C5
C12
C13
VD
C11
R1
L1
L2
L3
C10 50
Ω
OUT
50
Ω
C1
IN
C2
C3
C7
C8
C9
C1, C4, C10, C11
C2
C3
C5, C12
C6, C13
C7
C8
C9
L1
L2
L3
R1
R2
100 pF Chip Capacitor
22 pF Chip Capacitor
5 pF Chip Capacitor
1000 pF Chip Capacitor
1
µF
Chip Tantalum Capacitor
18 pF Chip Capacitor
10 pF Chip Capacitor
7 pF Chip Capacitor
8 Turns D: 0.5 mm,
φ
2.4 mm Enamel Wire
1 nH Chip Inductor
1.8 nH Chip Inductor
670
Ω
Chip Resistor
6.8 kΩ Chip Resistor
REJ03G1520-0100 Rev.1.00 Jul 04, 2007
Page 4 of 12
RQA0009TXDQS
Output Power, Drain Current
vs. Input Power
40
1.6
Pout
1.4
25
Power Gain, Power Added Efficiency
vs. Input Power
35
30
25
20
15
10
5
0
0
5
1.2
1.0
I
D
0.8
0.6
V
DS
= 6 V
f = 520 MHz
I
DQ
= 180 mA
10
15
20
25
0.4
0.2
0
30
Drain Current I
D
(A)
20
PG
80
15
PAE
10
V
DS
= 6 V
f = 520 MHz
I
DQ
= 180 mA
0
5
10
15
20
25
60
40
5
20
0
0
30
Input Power Pin (dBm)
Input Power Pin (dBm)
Power Gain, Power Added Efficiency
vs. Frequency
Input Return Loss vs. Frequency
Power Added Efficiency PAE (%)
20
PAE
15
PG
10
80
0
60
Input Return Loss RL (dB)
Power Gain PG (dB)
-5
40
-10
5
V
DS
= 6 V
I
DQ
= 180 mA
Pin = 25 dBm
470
490
510
530
20
-15
V
DS
= 6 V
I
DQ
= 180 mA
Pin = 25 dBm
470
490
510
530
550
0
450
0
550
-20
450
Frequency f (MHz)
Frequency f (MHz)
Power Gain, Power Added Efficiency,
vs. Drain to Source Voltage
Power Gain, Power Added Efficiency
vs. Idling Current
Power Added Efficiency PAE (%)
PAE
15
60
15
PG
10
75
PG
10
50
PAE
70
5
I
DQ
= 180 mA
f = 520 MHz
Pin = 25 dBm
4
5
6
7
8
9
40
5
V
DS
= 6 V
f = 520 MHz
Pin = 25 dBm
0.1
0.2
0.3
0.4
65
0
3
30
0
0
60
0.5
Drain to Source Voltage V
DS
(V)
Idling Current I
DQ
(A)
REJ03G1520-0100 Rev.1.00 Jul 04, 2007
Page 5 of 12
Power Added Efficiency PAE (%)
20
70
20
80
Power Gain PG (dB)
Power Gain PG (dB)
Power Added Efficiency PAE (%)
100
Pout (dBm)
Output Power
Power Gain PG (dB)
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