MC74VHC1G125,
MC74VHC1GT125
Noninverting 3-State Buffer
The MC74VHC1G125 / MC74VHC1GT125 is a single
non−inverting 3−state buffer in tiny footprint packages. The
MC74VHC1G125 has CMOS−level input thresholds while the
MC74VHC1GT125 has TTL−level input thresholds.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The input structures provide protection when voltages up to 5.5 V
are applied, regardless of the supply voltage. This allows the device to
be used to interface 5 V circuits to 3 V circuits. The output structures
also provide protection when V
CC
= 0 V and when the output voltage
exceeds V
CC
. These input and output structures help prevent device
destruction caused by supply voltage
−
input/output voltage mismatch,
battery backup, hot insertion, etc.
Features
www.onsemi.com
MARKING
DIAGRAMS
SC−88A
DF SUFFIX
CASE 419A
XX MG
G
•
•
•
•
•
•
Designed for 2.0 V to 5.5 V V
CC
Operation
3.5 ns t
PD
at 5 V (typ)
Inputs/Outputs Over−Voltage Tolerant up to 5.5 V
I
OFF
Supports Partial Power Down Protection
Source/Sink 8 mA at 3.0 V
Available in SC−88A, SC−74A, TSOP−5, SOT−553, SOT−953 and
UDFN6 Packages
•
Chip Complexity < 100 FETs
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
OE
A
EN
Y
SC−74A
DBV SUFFIX
CASE 318BQ
XXX MG
G
5
5
1
TSOP−5
DT SUFFIX
CASE 483
1
SOT−553
XV5 SUFFIX
CASE 463B
XX MG
G
XX MG
G
SOT−953
P5 SUFFIX
CASE 527AE
UDFN6
1.45 x 1.0
CASE 517AQ
XM
1
1
XM
Figure 1. Logic Symbol
UDFN6
1.0 x 1.0
CASE 517BX
XX
M
G
XM
1
= Specific Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
November, 2018
−
Rev. 18
1
Publication Order Number:
MC74VHC1G125/D
MC74VHC1G125, MC74VHC1GT125
OE
1
A
2
GND
3
Y
4
V
CC
5
A
1
GND
2
OE
3
Y
4
GND
(SC−88A/SOT−553/
TSOP−5/ SC−74A)
SOT−953
UDFN6
3
4
Y
A
2
5
NC
V
CC
5
OE
1
6
V
CC
Figure 2. Pinout
(Top View)
PIN ASSIGNMENT
(SC−88A/SOT−553/ TSOP−5/SC−74A)
Pin
1
2
3
4
5
Function
OE
A
GND
Y
V
CC
PIN ASSIGNMENT
(SOT−953)
Pin
1
2
3
4
5
Function
A
GND
OE
Y
V
CC
PIN ASSIGNMENT
(UDFN)
Pin
1
2
3
4
5
6
Function
OE
A
GND
Y
NC
V
CC
FUNCTION TABLE
Input
OE
L
L
H
X = Don’t Care
A
L
H
X
Output
Y
L
H
Z
www.onsemi.com
2
MC74VHC1G125, MC74VHC1GT125
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
DC Supply Voltage
DC Input Voltage
DC Output Voltage
TSOP−5, SC−88A (NLV)
Characteristics
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (V
CC
= 0 V)
Value
−0.5
to +7.0
−0.5
to +6.5
−0.5
to +7.0
−0.5
to +6.5
−0.5
to V
CC
+ 0.5
−0.5
to +7.0
−0.5
to +7.0
−0.5
to V
CC
+ 0.5
−0.5
to +6.5
−0.5
to +6.5
−20
±20
±25
±50
−65
to +150
260
+150
SC−88A
SC−74A
TSOP−5
SOT−553
SOT−953
UDFN6
SC−88A
SC−74A
TSOP−5
SOT−553
SOT−953
UDFN6
659
555
555
562
560
382
190
225
225
222
223
327
Level 1
Oxygen Index: 28 to 34
Human Body Model
Charged Device Model
UL 94 V−0 @ 0.125 in
2000
1000
$100
Unit
V
V
V
DC Output Voltage
Active−Mode (High or Low State)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
Tri−State Mode (Note 1)
Power−Down Mode (V
CC
= 0 V)
I
IK
I
OK
I
OUT
I
CC
or I
GND
T
STG
T
L
T
J
q
JA
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin or Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 secs
Junction Temperature Under Bias
Thermal Resistance (Note 2)
V
IN
< GND
V
OUT
< GND
V
mA
mA
mA
mA
°C
°C
°C
°C/W
P
D
Power Dissipation in Still Air
mW
MSL
F
R
V
ESD
I
Latchup
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage (Note 3)
Latchup Performance (Note 4)
−
−
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Applicable to devices with outputs that may be tri−stated.
2. Measured with minimum pad spacing on an FR4 board, using 10mm−by−1inch, 2 ounce copper trace no air flow.
3. HBM tested to ANSI/ESDA/JEDEC JS−001−2017. CDM tested to EIA/JESD22−C101−F. JEDEC recommends that ESD qualification to
EIA/JESD22−A115−A (Machine Model) be discontinued per JEDEC/JEP172A.
4. Tested to EIA/JESD78 Class II.
www.onsemi.com
3
MC74VHC1G125, MC74VHC1GT125
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
Positive DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Output Voltage
TSOP−5, SC−88A (NLV)
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
Active−Mode (High or Low State)
Tri−State Mode (Note 1)
Power−Down Mode (V
CC
= 0 V)
TSOP−5, SC−88A (NLV)
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
SC−74A, SC−88A, UDFN6, SOT−553, SOT−953
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
Characteristics
Min
2.0
0
0
0
0
0
−55
0
0
0
0
0
0
Max
5.5
5.5
V
CC
V
CC
5.5
5.5
+125
100
20
20
20
10
5
°C
ns/V
Unit
V
V
V
T
A
t
r
, t
f
Operating Temperature Range
Input Rise and Fall Time
Input Rise and Fall Time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
4
MC74VHC1G125, MC74VHC1GT125
DC ELECTRICAL CHARACTERISTICS (MC74VHC1G125)
Symbol
V
IH
Parameter
High−Level Input
Voltage
Test
Conditions
V
CC
(V)
2.0
3.0
4.5
5.5
V
IL
Low−Level Input
Voltage
2.0
3.0
4.5
5.5
V
OH
High−Level Output
Voltage
V
IN
= V
IH
or V
IL
I
OH
=
−50
mA
I
OH
=
−50
mA
I
OH
=
−50
mA
I
OH
=
−4
mA
I
OH
=
−8
mA
V
IN
= V
IH
or V
IL
I
OL
= 50
mA
I
OL
= 50
mA
I
OL
= 50
mA
I
OL
= 4 mA
I
OL
= 8 mA
V
IN
= 5.5 V or
GND
V
OUT
= 0 V to
5.5 V
V
IN
= 5.5 V or
V
OUT
= 5.5 V
V
IN
= V
CC
or
GND
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
1.65
to 5.5
5.5
0
5.5
T
A
= 25°C
Min
1.5
2.1
3.15
3.85
−
−
−
−
1.9
2.9
4.4
2.58
3.94
−
−
−
−
−
−
−
−
−
Typ
−
−
−
−
−
−
−
−
2.0
3.0
4.5
−
−
0.0
0.0
0.0
−
−
−
−
−
−
Max
−
−
−
−
0.5
0.9
1.35
1.65
−
−
−
−
−
0.1
0.1
0.1
0.36
0.36
±0.1*
±0.25
1.0
1.0
−40°C
≤
T
A
≤
85°C
Min
1.5
2.1
3.15
3.85
−
−
−
−
1.9
2.9
4.4
2.48
3.80
−
−
−
−
−
−
−
−
−
Max
−
−
−
−
0.5
0.9
1.35
1.65
−
−
−
−
−
0.1
0.1
0.1
0.44
0.44
±1.0
$2.5
10
20
−55°C
≤
T
A
≤
125°C
Min
1.5
2.1
3.15
3.85
−
−
−
−
1.9
2.9
4.4
2.34
3.66
−
−
−
−
−
−
−
−
−
Max
−
−
−
−
0.5
0.9
1.35
1.65
−
−
−
−
−
0.1
0.1
0.1
0.52
0.52
$1.0
$2.5
10
40
V
V
Unit
V
V
OL
Low−Level Output
Voltage
V
I
IN
I
OZ
I
OFF
I
CC
Input Leakage
Current
3−State Output
Leakage Current
Power Off Leakage
Current
Quiescent Supply
Current
mA
mA
mA
mA
*Guaranteed by design.
www.onsemi.com
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
