Programmable Clock Generator
5P49V5908
DATASHEET
Description
The 5P49V5908 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock
®
5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I C
addresses to allow multiple devices to be used in a system.
2
Features
•
Generates up to four independent output frequencies with a
•
total of 11 differential outputs and one reference output
Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency
of each output pair can be individually programmed
– Eight copies of Low Power HCSL(LP-HCSL) outputs.
Programmable frequency
– See Output Features and Descriptions for details
•
One reference LVCMOS output clock
•
High performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Pin Assignment
OUT0_SEL_I2CB
OE_buffer
V
DD
•
Four fractional output dividers (FODs)
•
Independent Spread Spectrum capability from each
OUT11B
OUT11
OUT1B
V
DDO
1
V
DDO
OUT1
OUT10
V
DDO
0
•
•
•
V
DDO
2
OUT2
OUT2B
OEB
7_10
NC
V
DD
V
DD_CORE
OUT3
OUT3B
V
DDO
NC
NC
OUT10B
XOUT
XIN/REF
V
DDA
V
DDO
OUT9
OUT9B
OUT8
OUT8B
OUT7
OUT7B
SD/OE
1
2
3
4
5
6
7
8
9
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
fractional output divider (FOD)
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
NC
•
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
EPAD
31
30
29
28
27
26
10
11
12
13 14 15 16 17 18
25
19 20 21 22 23 24
•
•
•
•
SEL0/SCL
SEL1/SD
OEB
3,11
V
DDO
OUT5
OUT5B
OUT4
OUT6B
OUT4B
OUT6
V
DD
V
DDO
4
Programmable loop bandwidth
Programmable crystal load capacitance
Power-down mode
Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 8 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
48-pin VFQFPN
•
Available in 48-pin VFQFPN package (NDG48)
•
-40° to +85°C industrial temperature operation
5P49V5908 MARCH 10, 2017
1
©2017 Integrated Device Technology, Inc.
5P49V5908 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
V
DDO
1
SD/OE
SEL1/SDA
SEL0/SCL
OTP
and
Control Logic
V
DDO
0
OUT0_SEL_I2CB
OUT1
FOD1
OUT1B
V
DDO
2
OUT2
FOD2
OUT2B
PLL
OEB
3,11
FOD3
OUT3, 5, 6, 11
OEB
7_10
OUT7 - 10
V
DDA
V
DDO
OE_buffer
V
DD
V
DD_CORE
V
DDO
4
OUT4
FOD4
OUT4B
Typical Applications
•
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
PROGRAMMABLE CLOCK GENERATOR
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MARCH 10, 2017
5P49V5908 DATASHEET
Table 1:Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
Name
OUT10B
XOUT
XIN/REF
VDDA
VDDO
OUT9
OUT9B
OUT8
OUT8B
OUT7
OUT7B
SD/OE
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Input
Type
Description
Complementary output clock 10. Low-Power HCSL (LP-HCSL) output.
Crystal oscillator interface output.
Crystal oscillator interface input, or single-ended LVCMOS clock input. Ensure that the
input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF Interface”.
Analog functions power supply pin. Connect to 1.8V.
Connect to 1.8V. Power pin for outputs 3, 5-11.
Output clock 9. Low-Power HCSL (LP-HCSL) output.
Complementary output clock 9. Low-Power HCSL (LP-HCSL) output.
Output clock 8. Low-Power HCSL (LP-HCSL) output.
Complementary output clock 8. Low-Power HCSL (LP-HCSL) output.
Output clock 7. Low-Power HCSL (LP-HCSL) output.
Complementary output clock 7. Low-Power HCSL (LP-HCSL) output.
Internal Pull- Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit controls the
down
configuration of the SD/OE pin. The SH bit needs to be high for SD/OE pin to be configured
as SD. The SP bit (0x02) controls the polarity of the signal to be either active HIGH or LOW
only when pin is configured as OE (Default is active LOW.) Weak internal pull down resistor.
When configured as SD, device is shut down, differential outputs are driven high/low, and the
single-ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the
programming bits as shown in the SD/OE Pin Function Truth table.
Internal Pull- Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB. Weak internal
down
pull down resistor.
Internal Pull- Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB. Weak internal
down
pull down resistor.
Connect to 1.8V.
Connect to 1.8V. Power pin for outputs 3, 5-11.
Output Clock 6. Low-Power HCSL (LP-HCSL) output.
Complementary Output Clock 6. Low-Power HCSL (LP-HCSL) output.
Output Clock 5. Low-Power HCSL (LP-HCSL) output.
Complementary output clock 5. Low-Power HCSL (LP-HCSL) output.
Connect to 1.8V to 3.3V. VDD supply for OUT4.
Output clock 4. Please refer to the Output Drivers section for more details.
Complementary output clock 4. Please refer to the Output Drivers section for more details.
Internal Pull- Active low Output Enable pin for Outputs 3, 5, 6, 11.
down
1 = disable outputs, 0 = enable outputs. This pin has internal pull-down.
Do not connect.
—
Do not connect.
—
Connect to 1.8V. Power pin for outputs 3, 5-11.
Complementary output Clock 3. Low-Power HCSL (LP-HCSL) output.
Output clock 3. Low-Power HCSL (LP-HCSL) output.
Connect to 1.8V.
Connect to 1.8V.
Do not connect.
Internal Pull- Active low Output Enable pin for Outputs 7-10.
down
1 = disable outputs, 0 = enable outputs. This pin has internal pull-down.
Complementary output clock 2. Please refer to the Output Drivers section for more details.
Output clock 2. Please refer to the Output Drivers section for more details.
Connect to 1.8V to 3.3V. VDD supply for OUT2
Complementary output clock 1. Please refer to the Output Drivers section for more details.
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SEL1/SDA
SEL0/SCL
VDD
VDDO
OUT6
OUT6B
OUT5
OUT5B
VDDO4
OUT4
OUT4B
OEB
3,11
NC
NC
VDDO
OUT3B
OUT3
VDD_Core
VDD
NC
OEB
7_10
OUT2B
OUT2
VDDO2
OUT1B
Input
Input
Power
Power
Output
Output
Output
Output
Power
Output
Output
Input
Input
Input
Power
Output
Output
Power
Power
Input
Input
Output
Output
Power
Output
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PROGRAMMABLE CLOCK GENERATOR
5P49V5908 DATASHEET
Pin Descriptions (cont.)
Number
38
39
40
41
42
43
44
45
46
47
Name
OUT1
VDDO1
NC
OUT11
OUT11B
VDDO
VDD
OE_buffer
VDDO0
OUT0_SEL_I2CB
Output
Power
Input
Output
Output
Power
Power
Input
Power
Output
—
Type
Description
Output clock 1. Please refer to the Output Drivers section for more details.
Connect to 1.8V to 3.3V. VDD supply for OUT1
Do not connect.
Output clock 11. Low-Power HCSL(LP-HCSL) output.
Complementary output clock 11. Low-Power HCSL(LP-HCSL) output.
Connect to 1.8V. Power pin for outputs 3, 5-11
Connect to 1.8V
Internal Pull- Active High Output enable for outputs 3, 5-11.
up
0 = disable outputs, 1=enable outputs. This pin has internal pull-up.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output voltage levels
for OUT0.
Internal Pull- Latched input/LVCMOS Output. At power up, the voltage at the pin
down
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 13
and 14. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 13 and
14 will be configured as hardware select pins, SEL1 and SEL0. If a weak pull
down (10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 13 and
14 will act as the SDA and SCL pins of an I2C interface. After power up, the pin
acts as a LVCMOS reference output.
Output clock 10. Low-Power HCSL (LP-HCSL) output.
Connect to ground pad.
48
EPAD
OUT10
GND
Output
GND
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5908 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5908 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output divider and any spread amount from
±0.25% to ±2.5% center spread and -0.5% to -5% down
spread.
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
OUT0_SEL_I2CB SEL1 SEL0
I
2
C
REG0:7 Config
@ POR
Access
1
1
1
1
0
0
0
1
1
X
X
0
1
0
1
X
X
No
No
No
No
Yes
Yes
0
0
0
0
1
0
0
1
2
3
I2C
defaults
0
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Frequency–Fref
(MHz)
5
350
0
Loop
Bandwidth Min
(kHz)
40
300
Loop
Bandwidth Max
(kHz)
126
1000
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDA power supply so that they ramp with that
supply or are tied low (this is the same as floating the pins).
This will cause the register configuration to be loaded that is
selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7=0, after
the first 10ms of operation the levels of the SELx pins can be
changed, either to low or to the same level as VDDA. The
SELx pins must be driven with a digital signal of < 300ns
Rise/Fall time and only a single pin can be changed at a time.
After a pin level change, the device must not be interrupted for
at least 1ms so that the new values have time to load and take
effect.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
PROGRAMMABLE CLOCK GENERATOR
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MARCH 10, 2017
5P49V5908 DATASHEET
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
A crystal manufacturer will calibrate its crystals to the nominal
frequency with a certain load capacitance value. When the
oscillator load capacitance matches the crystal load
capacitance, the oscillation frequency will be accurate. When
the oscillator load capacitance is lower than the crystal load
capacitance, the oscillation frequency will be higher than
nominal and vice versa so for an accurate oscillation
frequency you need to make sure to match the oscillator load
capacitance with the crystal load capacitance.
To set the oscillator load capacitance there are two tuning
capacitors in the IC, one at XIN and one at XOUT. They can
be adjusted independently but commonly the same value is
used for both capacitors. The value of each capacitor is
composed of a fixed capacitance amount plus a variable
capacitance amount set with the XTAL[5:0] register.
Adjustment of the crystal tuning capacitors allows for
maximum flexibility to accommodate crystals from various
manufacturers. The range of tuning capacitor values available
are in accordance with the following table.
You can write the following equations for the total capacitance
at each crystal pin:
C
XIN
= Ci
1
+ Cs
1
+ Ce
1
C
XOUT
= Ci
2
+ Cs
2
+ Ce
2
Ci
1
and Ci
2
are the internal, tunable capacitors. Cs
1
and Cs
2
are stray capacitances at each crystal pin and typical values
are between 1pF and 3pF.
Ce
1
and Ce
2
are additional external capacitors that can be
added to increase the crystal load capacitance beyond the
tuning range of the internal capacitors. However, increasing
the load capacitance reduces the oscillator gain so please
consult the factory when adding Ce
1
and/or Ce
2
to avoid
crystal startup issues. Ce
1
and Ce
2
can also be used to adjust
for unpredictable stray capacitance in the PCB.
The final load capacitance of the crystal:
CL = C
XIN
× C
XOUT
/ (C
XIN
+ C
XOUT
)
For most cases it is recommended to set the value for
capacitors the same at each crystal pin:
C
XIN
= C
XOUT
= Cx
→
CL = Cx / 2
The complete formula when the capacitance at both crystal
pins is the same:
CL = (9pF + 0.5pF × XTAL[5:0] + Cs + Ce) / 2
Example 1:
The crystal load capacitance is specified as 8pF
and the stray capacitance at each crystal pin is Cs=1.5pF.
Assuming equal capacitance value at XIN and XOUT, the
equation is as follows:
8pF = (9pF + 0.5pF × XTAL[5:0] + 1.5pF) / 2
→
0.5pF × XTAL[5:0] = 5.5pF
→
XTAL[5:0] = 11 (decimal)
Example 2:
The crystal load capacitance is specified as 12pF
and the stray capacitance Cs is unknown. Footprints for
external capacitors Ce are added and a worst case Cs of 5pF
is used. For now we use Cs + Ce = 5pF and the right value for
Ce can be determined later to make 5pF together with Cs.
12pF = (9pF + 0.5pF × XTAL[5:0] + 5pF) / 2
→
XTAL[5:0] = 20 (decimal)
XTAL[5:0] Tuning Capacitor Characteristics
Parameter
XTAL
Bits
6
Step (pF)
0.5
Min (pF)
9
Max (pF)
25
The capacitance at each crystal pin inside the chip starts at
9pF with setting 000000b and can be increased up to 25pF
with setting 111111b. The step per bit is 0.5pF.
You can write the following equation for this capacitance:
Ci = 9pF + 0.5pF × XTAL[5:0]
The PCB where the IC and the crystal will be assembled adds
some stray capacitance to each crystal pin and more
capacitance can be added to each crystal pin with additional
external capacitors.
MARCH 10, 2017
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PROGRAMMABLE CLOCK GENERATOR
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