PIC18(L)F26/27/45/46/47/55/56/57K42
28/40/44/48-Pin, Low-Power High-Performance
Microcontrollers with XLP Technology
Description
The PIC18(L)F26/27/45/46/47/55/56/57K42 microcontrollers are available in 28/40/44/48-pin devices. These devices
feature a 12-bit ADC with Computation (ADC
2
) automating Capacitive Voltage Divider (CVD) techniques for advanced
touch sensing, averaging, filtering, oversampling and threshold comparison, Temperature Sensor, Vectored Interrupt
Controller with fixed latency for handling interrupts, System Bus Arbiter, Direct Memory Access capabilities, UART with
support for Asynchronous, DMX, DALI and LIN transmissions, SPI, I
2
C, memory features like Memory Access Partition
(MAP) to support customers in data protection and bootloader applications, and Device Information Area (DIA) which
stores factory calibration values to help improve temperature sensor accuracy.
Core Features
• C Compiler Optimized RISC Architecture
• Operating Speed:
- Up to 64 MHz clock input
- 62.5 ns minimum instruction cycle
• Two Direct Memory Access (DMA) Controllers
- Data transfers to SFR/GPR spaces from
either Program Flash Memory, Data
EEPROM or SFR/GPR spaces
- User-programmable source and destination
sizes
- Hardware and software-triggered data
transfers
• System Bus Arbiter with User-Configurable
Priorities for Scanner and DMA1/DMA2 with
respect to the main line and interrupt execution
• Vectored Interrupt Capability
- Selectable high/low priority
- Fixed interrupt latency
- Programmable vector table base address
• 31-Level Deep Hardware Stack
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT)
- Variable prescaler selection
- Variable window size selection
- Configurable in hardware or software
Memory
Up to 128 KB Flash Program Memory
Up to 8 KB Data SRAM Memory
Up to 1 KB Data EEPROM
Memory Access Partition (MAP)
- Configurable boot and app region sizes with
individual write-protections
• Programmable Code Protection
• Device Information Area (DIA) stores:
- Unique IDs and Device IDs
- Temp Sensor factory-calibrated data
- Fixed Voltage Reference calibrated data
• Device Configuration Information (DCI) stores:
- Erase row size
- Number of write latches per row
- Number of user rows
- Data EEPROM memory size
- Pin count
•
•
•
•
Operating Characteristics
• Operating Voltage Range:
- 1.8V to 3.6V (PIC18LF26/27/45/46/55/56/
57K42)
- 2.3V to 5.5V (PIC18F26/27/45/46/47/55/56/
57K42)
• Temperature Range:
- Industrial: -40°C to 85°C
- Extended: -40°C to 125°C
Power-Saving Functionality
• DOZE mode: Ability to run CPU core slower than
the system clock
• IDLE mode: Ability to halt CPU core while internal
peripherals continue operating
• SLEEP mode: Lowest power consumption
• Peripheral Module Disable (PMD):
- Ability to disable unused peripherals to
minimize power consumption
2017 Microchip Technology Inc.
Preliminary
DS40001919B-page 1
PIC18(L)F26/27/45/46/47/55/56/57K42
eXtreme Low-Power (XLP) Features
• Sleep mode: 60 nA @ 1.8V, typical
• Windowed Watchdog Timer: 720 nA @ 1.8V,
typical
• Secondary Oscillator: 580 nA @ 32 kHz
• Operating Current:
- 5 uA @ 32 kHz, 1.8V, typical
- 65 uA/MHz @ 1.8V, typical
• One SPI module:
- Configurable length bytes
- Configurable length data packets
- Receive-without-transmit option
- Transmit-without-receive option
- Transfer byte counter
- Separate Transmit and Receive Buffers with
2-byte FIFO and DMA capabilities
• Two I
2
C modules, SMBus, PMBus™ compatible:
- Supports Standard-mode (100 kHz), Fast-
mode (400 kHz) and Fast-mode plus (1 MHz)
modes of operation
- Dedicated Address, Transmit and Receive
buffers
- Bus Collision Detection with arbitration
- Bus time-out detection and handling
- Multi-Master mode
- Separate Transmit and Receive Buffers with
2-byte FIFO and DMA capabilities
- I
2
C, SMBus 2.0 and SMBus 3.0, and 1.8V
input level selections
• Device I/O Port Features:
- 24 I/O pins (PIC18(L)F2xK42)
- 35 I/O pins (PIC18(L)F4xK42)
- 43 I/O pins (PIC18(L)F5xK42)
- One input-only pin (RE3)
- Individually programmable I/O direction,
open-drain, slew rate, weak pull-up control
- Interrupt-on-change (on up to 25 I/O pins)
- Three External Interrupt Pins
• Peripheral Pin Select (PPS):
- Enables pin mapping of digital I/O
• Signal Measurement Timer (SMT):
- 24-bit timer/counter with prescaler
Digital Peripherals
• Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT)
- Hardware monitoring and Fault detection
• Four 16-Bit Timers (TMR0/1/3/5)
• Four Configurable Logic Cell (CLC):
- Integrated combinational and sequential logic
• Three Complementary Waveform Generators
(CWGs):
- Rising and falling edge dead-band control
- Full-bridge, half-bridge, 1-channel drive
- Multiple signal sources
- Programmable dead band
- Fault-shutdown input
• Four Capture/Compare/PWM (CCP) modules
• Four 10-bit Pulse-Width Modulators (PWMs)
• Numerically Controlled Oscillator (NCO):
- Generates true linear frequency control
- High resolution using 20-bit accumulator and
20-bit increment values
• DSM: Data Signal Modulator
- Multiplex two carrier clocks, with glitch
prevention feature
- Multiple sources for each carrier
• Programmable CRC with Memory Scan:
- Reliable data/program memory monitoring for
fail-safe operation (e.g., Class B)
- Calculate CRC over any portion of program
memory or data EEPROM
• Two UART Modules:
- Modules are asynchronous and compatible
with RS-232 and RS-485
- One of the UART modules supports LIN
Master and Slave, DMX-512 mode, DALI
Gear and Device protocols
- Automatic and user-timed BREAK period
generation
- DMA Compatible
- Automatic checksums
- Programmable 1, 1.5, and 2 Stop bits
- Wake-up on BREAK reception
2017 Microchip Technology Inc.
Preliminary
DS40001919B-page 2
PIC18(L)F26/27/45/46/47/55/56/57K42
Analog Peripherals
• Analog-to-Digital Converter with Computation
(ADC
2
):
- 12-bit with up to 35 external channels
- Automated post-processing
- Automated math functions on input signals:
averaging, filter calculations, oversampling
and threshold comparison
- Operates in Sleep
- Integrated charge pump for improved low-
voltage operation
• Hardware Capacitive Voltage Divider (CVD):
- Automates touch sampling and reduces
software size and CPU usage when touch or
proximity sensing is required
- Adjustable sample and hold capacitor array
- Two guard ring output drives
• Temperature Sensor
- Internal connection to ADC
- Can be calibrated for improved accuracy
• Two Comparators:
- Low-Power/High-Speed mode
- Fixed Voltage Reference at noninverting
input(s)
- Comparator outputs externally accessible
• 5-bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive Reference Selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference
- Fixed Voltage Reference with 1.024V, 2.048V
and 4.096V output levels
Flexible Oscillator Structure
• High-Precision Internal Oscillator
- Selectable frequency range up to 64 MHz
- ±1% at calibration (nominal)
• Low-Power Internal 32 kHz Oscillator
(LFINTOSC)
• External 32 kHz Crystal Oscillator (SOSC)
• External Oscillator Block with:
- x4 PLL with external sources
- Three crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor
• Oscillator Start-up Timer (OST)
- Ensures stability of crystal oscillator sources
2017 Microchip Technology Inc.
Preliminary
DS40001919B-page 3
PIC18(L)F2X/4X/5XK42 FAMILY TYPES
8-bit/ (with HLT) /16-bit Timer
Direct Memory Access (DMA)
(ch)
Program Flash Memory (KB)
Signal Measurement Timer
(SMT)
Peripheral Module Disable
Memory Access Partition
Window Watchdog Timer
(WWDT)
2016-2017 Microchip Technology Inc.
Peripheral Pin Select
Vectored Interrupts
Data SRAM (bytes)
Zero-Cross Detect
Data EEPROM (B)
Data Sheet Index
CCP/10-bit PWM
Comparator
12-bit ADC
2
(ch)
5-bit DAC
Device
Debug
(1)
I/O Pins
I
2
C/SPI
UART
CWG
NCO
CLC
PIC18(L)F26/27/45/46/47/55/56/57K42
PIC18(L)F24K42
PIC18(L)F25K42
PIC18(L)F26K42
PIC18(L)F27K42
PIC18(L)F45K42
PIC18(L)F46K42
PIC18(L)F47K42
PIC18(L)F55K42
PIC18(L)F56K42
PIC18(L)F57K42
Note 1:
Data Sheet Index:
A
A
B
B
B
B
B
B
B
B
16
32
64
128
32
64
128
32
64
128
256
256
1024
1024
256
1024
1024
256
1024
1024
1024
2048
4096
8192
2048
4096
8192
2048
4096
8192
25
25
25
25
36
36
36
44
44
44
24
24
24
24
35
35
35
43
43
43
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
3/4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
4/4
3
3
3
3
3
3
3
3
3
3
1
1
1
1
1
1
1
1
1
1
4
4
4
4
4
4
4
4
4
4
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
2
2
2
2
2
2
2
2
2
2
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
I
I
I
I
I
I
I
I
I
I
Preliminary
DS40001919B-page 4
I – Debugging integrated on chip.
Unshaded devices are not described in this document.
A:
B:
Note:
DS40001869
DS40001919
PIC18(L)F24/25K42 Data Sheet, 28-Pin
PIC18(L)F26/27/45/46/47/55/56/57K42 Data Sheet, 28/40/44/48-Pin
For other small form-factor package availability and marking information, visit
http://www.microchip.com/packaging
or contact your local sales office.
PIC18(L)F26/27/45/46/47/55/56/57K42
Pin Diagrams
28-pin SPDIP, SOIC, SSOP
V
PP
/MCLR/RE3
RA0
RA1
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
RC0
RC1
RC2
RC3
1
2
3
4
PIC18(L)F2XK42
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
RC6
RC5
RC4
Note:
See
Table 1
for location of all peripheral functions.
28-pin QFN (6x6x0.9mm), UQFN (6x6x0.5mm)
RA1
RA0
RE3/MCLR/V
PP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
28 27 26 25 24 23 22
RA2
RA3
RA4
RA5
V
SS
RA7
RA6
1
2
3
4
5
6
7
21
20
19
18
17
16
15
RB3
RB2
RB1
RB0
V
DD
V
SS
RC7
PIC18(L)F2XK42
8 9 10 11 12 13 14
RC0
RC1
RC2
RC3
RC4
RC5
RC6
Note 1:
See
Table 1
for location of all peripheral functions.
2:
It is recommended that the exposed bottom pad be connected to V
SS
, however it must not be the
only V
SS
connection to the device.
2017 Microchip Technology Inc.
Preliminary
DS40001919B-page 5
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