Dual 1:4, LVDS Output Fanout Buffer
8SLVD2104
DATA SHEET
General Description
The 8SLVD2104 is a high-performance differential dual 1:4 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2104 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2104 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with four low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Two 1:4, low skew, low additive jitter LVDS fanout buffers
• Two differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS and LVPECL
• Maximum input clock frequency: 2GHz
• Output bank skew: 35ps, (maximum)
• Propagation delay: 300ps, (maximum)
• Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz):
105fs, (maximum)
• 2.5V supply voltage
• Lead-free (RoHS 6) 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
nQB2
nQB1
QB1
nQB0
QB2
QB0
V
DD
GND
QB3
nQB3
EN
PCLKB
nPCLKB
V
REFB
1
2
3
4
5
6
7
8
V
DD
28 27 26 25 24 23 22
21
20
nQA3
QA3
nQA2
QA2
nQA1
QA1
V
DD
8SLVD2104
19
18
17
16
15
9 10 11 12 13 14
V
REFA
nQA0
PCLKA
nPCLKA
GND
QA0
28-Lead, 5mm x 5mm VFQFN
8SLVD2104 REVISION 1 08/03/15
1
©2015 Integrated Device Technology, Inc.
8SLVD2104 DATA SHEET
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12,
13
14
15
16
17
18,
19
20
21
22
23
24
25
26
27
28
Name
GND
QB3
nQB3
EN
PCLKB
nPCLKB
V
REFB
V
DD
PCLKA
nPCLKA
V
REFA
QA0
nQA0
GND
V
DD
QA1
nQA1
QA2
nQA2
QA3
nQA3
QB0
nQB0
QB1
nQB1
QB2
nQB2
V
DD
ePAD
Power
Output
Differential output pair B3. LVDS interface levels.
Output
Input
Input
Input
Output
Power
Input
Input
Output
Output
Differential output pair A0. LVDS interface levels.
Output
Power
Power
Output
Differential output pair A1. LVDS interface levels.
Output
Output
Differential output pair A2. LVDS interface levels.
Output
Output
Differential output pair A3. LVDS interface levels.
Output
Output
Differential output pair B0. LVDS interface levels.
Output
Output
Differential output pair B1. LVDS interface levels.
Output
Output
Differential output pair B2. LVDS interface levels.
Output
Power
Power supply pin.
Thermal pad. Connect to ground.
Power supply ground.
Power supply pin.
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Output enable pin. V
DD
/2 default when left floating.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Bias voltage reference for the PCLKB, nPCLKB input pair.
Power supply pin.
Non-inverting differential clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Bias voltage reference for the PCLKA, nPCLKA input pair.
Type
Description
Power supply ground.
NOTE 1:
Pulldown
and
Pullup
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
2
REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown
Resistor
Input Pullup
Resistor
EN,
PCLK[A:B],
nPCLK[A:B]
EN,
nPCLK[A:B]
Test Conditions
Minimum
Typical
2
51
Maximum
Units
pF
k
R
PULLUP
51
k
Function Table
Table 3. EN Input Selection Function Table
1
Input
EN
0 (Low)
1 (High)
Open
Operation
Outputs are disabled and static at Qx = 0 (low level) and nQx = 1 (high level).
Bank A outputs are enabled and Bank B outputs are disabled at the following static levels:
QBx = 0 (low level) and nQBx = 1 (high level).
All outputs enabled.
NOTE 1: EN is an asynchronous control input pin.
REVISION 1 08/03/15
3
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
8SLVD2104 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Electrical Characteristics
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model
1
ESD - Charged Device Model
1
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
125C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
1
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
All outputs terminated with 100 in
between nQx, Qx; DC to 2GHz
Test Conditions
Minimum
2.375
Typical
2.5
145
Maximum
2.625
170
Units
V
mA
NOTE 1: Qx, nQx denotes QA[3:0], nQA[3:30], and QB[3:0], nQB[3:0].
Table 4B. LVCMOS/LVTTL Input Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
MID
V
IH
V
IL
I
IH
I
IL
Parameter
Input Voltage -
Open Pin
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
EN
EN
EN
EN
EN
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-150
Test Conditions
Open
0.7 * V
DD
-0.3
Minimum
Typical
V
DD
/ 2
V
DD
+ 0.3
0.2 * V
DD
150
Maximum
Units
V
V
V
µA
µA
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
4
REVISION 1 08/03/15
8SLVD2104 DATA SHEET
Table 4C. Differential Input Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REFA,
V
REFB
V
PP
V
CMR
Parameter
Input High
Current
Input Low
Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.625V, V
IN
= 0V
V
DD
= 2.5V; I
REF
= +100µA
f
REF
< 1.5 GHz
f
REF
> 1.5 GHz
Common Mode Input Voltage
1, 2
-10
-150
1.0
0.15
0.2
1.0
1.35
1.6
1.6
V
DD
– V
PP
/2
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
Reference Voltages
for Input Bias
Peak-to-Peak Voltage
1
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined at the crosspoint.
,
Table 4D. LVDS Output DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
1, 2
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.0
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.4
50
Units
mV
mV
V
mV
NOTE 1: Qx, nQx denotes QA[3:0], nQA[3:30], and QB[3:0], nQB[3:0].
NOTE 2: 100 termination across differential outputs.
REVISION 1 08/03/15
5
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
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