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MB95F563KWQN-G-SNERE1

Description
8-bit microcontroller-MCU MM MCU
Categorysemiconductor    The embedded processor and controller    Micro - MCU controller    8-bit microcontroller - MCU   
File Size3MB,89 Pages
ManufacturerCypress Semiconductor
Environmental Compliance
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MB95F563KWQN-G-SNERE1 Overview

8-bit microcontroller-MCU MM MCU

MB95F563KWQN-G-SNERE1 Parametric

Parameter NameAttribute value
MakerCypress Semiconductor
Product Category8-bit microcontroller-MCU
seriesMB95560H
EncapsulationCut Tape
EncapsulationReel
Factory packaging quantity5000
MB95560H Series
MB95570H Series
MB95580H Series
New 8FX 8-bit Microcontrollers
The MB95560H/570H/580H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the
microcontrollers of this series contain a variety of peripheral resources.
Features
F
2
MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Clock (The main oscillation clock and the suboscillation clock
are only available on MB95F562H/F562K/F563H/F563K/
F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.)
Selectable main clock source
• Main oscillation clock (up to 16.25 MHz, maximum ma-
chine clock frequency: 8.125 MHz)
• External clock (up to 32.5 MHz, maximum machine clock
frequency: 16.25 MHz)
• Main CR clock (4 MHz
2%)
- The main CR clock frequency becomes 8 MHz when
the PLL multiplication rate is 2.
- The main CR clock frequency becomes 10 MHz when
the PLL multiplication rate is 2.5.
- The main CR clock frequency becomes 12 MHz when
the PLL multiplication rate is 3.
- The main CR clock frequency becomes 16 MHz when
the PLL multiplication rate is 4.
Selectable subclock source
• Suboscillation clock (32.768 kHz)
• External clock (32.768 kHz)
• Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
Timer
8/16-bit composite timer
2 channels (only one channel on
MB95F572H/F572K/F573H/F573K/F574H/F574K/F582H/
F582K/F583H/F583K/F584H/F584K)
Time-base timer
1 channel
Watch prescaler
1 channel
LIN-UART (only available on MB95F562H/F562K/F563H/
F563K/F564H/F564K/F582H/F582K/F583H/F583K/F584H/
F584K)
Full duplex double buffer
Capable of clock synchronous serial data transfer and clock
asynchronous serial data transfer
External interrupt
Interrupt by edge detection (rising edge, falling edge, and
both edges can be selected)
Can be used to wake up the device from different low power
consumption (standby) modes
8/10-bit A/D converter
There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
In standby mode, the device can be made to enter either
normal standby mode or deep standby mode.
I/O port
MB95F562H/F563H/F564H (maximum no. of I/O ports: 16)
- General-purpose I/O ports (CMOS I/O): 15
- General-purpose I/O ports (N-ch open drain): 1
- General-purpose I/O ports (CMOS I/O): 15
- General-purpose I/O ports (N-ch open drain): 2
- General-purpose I/O ports (CMOS I/O): 3
- General-purpose I/O ports (N-ch open drain): 1
- General-purpose I/O ports (CMOS I/O): 3
- General-purpose I/O ports (N-ch open drain): 2
- General-purpose I/O ports (CMOS I/O): 11
- General-purpose I/O ports (N-ch open drain): 1
- General-purpose I/O ports (CMOS I/O): 11
- General-purpose I/O ports (N-ch open drain): 2
MB95F562K/F563K/F564K (maximum no. of I/O ports: 17)
MB95F572H/F573H/F574H (maximum no. of I/O ports: 4)
MB95F572K/F573K/F574K (maximum no. of I/O ports: 5)
MB95F582H/F583H/F584H (maximum no. of I/O ports: 12)
MB95F582K/F583K/F584K (maximum no. of I/O ports: 13)
On-chip debug
1-wire serial control
Serial writing supported (asynchronous mode)
Hardware/software watchdog timer
Built-in hardware watchdog timer
Built-in software watchdog timer
Power-on reset
A power-on reset is generated when the power is switched
on.
Low-voltage detection reset circuit (only available on
MB95F562K/F563K/F564K/F572K/F573K/F574K/F582K/
F583K/F584K)
Built-in low-voltage detector
Clock supervisor counter
Built-in clock supervisor counter function
Dual operation Flash memory
The program/erase operation and the read operation can be
executed in different banks (upper bank/lower bank) simul-
taneously.
Flash memory security function
Protects the content of the Flash memory.
8-bit or 10-bit resolution can be selected.
Low power consumption (standby) modes
Cypress Semiconductor Corporation
Document Number: 002-04629 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 21, 2017
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