MCIMX7D2DVK12SD datasheet, PDF

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MCIMX7D2DVK12SD: DescriptionProcessor - Application-specific i.MX 7 series 32-bit MPU, Dual ARM Cortex-A7 core, 1.2GHz, MAPBGA 488; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，159 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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MCIMX7D2DVK12SD Overview

Processor - Application-specific i.MX 7 series 32-bit MPU, Dual ARM Cortex-A7 core, 1.2GHz, MAPBGA 488

MCIMX7D2DVK12SD Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
package instruction	TFBGA,
Reach Compliance Code	compliant
Other features	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE
Address bus width	16
bit size	32
boundary scan	YES
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B488
length	12 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	488
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Maximum seat height	1.1 mm
speed	1200 MHz
Maximum supply voltage	1.25 V
Minimum supply voltage	1.2 V
Nominal supply voltage	1.225 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.4 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	12 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

User Manual

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NXP Semiconductors

Data Sheet: Technical Data

Document Number: IMX7DCEC

Rev. 5, 07/2017

MCIMX7DxDxxxxxD

MCIMX7DxExxxxxD

i.MX 7Dual Family of

Applications Processors

Datasheet

Package Information

Plastic Package

BGA 12 x 12 mm, 0.4 mm pitch

BGA 19 x 19 mm, 0.75 mm pitch

Ordering Information

See

Table 1 on page 3

i.MX 7Dual introduction

The i.MX 7Dual family of processors represents NXP’s

latest achievement in high-performance processing for

low-power requirements with a high degree of functional

integration. These processors are targeted towards the

growing market of connected and portable devices.

The i.MX 7Dual family of processors features advanced

implementation of the ARM® Cortex®-A7 core, which

operates at speeds of up to 1 GHz and 1.2 GHz,

depending on the part number. The i.MX 7Dual family

provides up to 32-bit

DDR3/DDR3L/LPDDR2/LPDDR3-1066 memory

interface and a number of other interfaces for connecting

peripherals, such as WLAN, Bluetooth, GPS, displays,

and camera sensors.

i.MX 7Solo introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Ordering information. . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

2.1 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.1 Special signal considerations . . . . . . . . . . . . . . . . .15

3.2 Recommended connections for unused analog

interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .19

4.1 Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . .19

4.2 Integrated LDO voltage regulator parameters . . . .34

4.3 PLL electrical characteristics . . . . . . . . . . . . . . . . .36

4.4 On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . .36

4.5 I/O DC parameters . . . . . . . . . . . . . . . . . . . . . . . . .37

4.6 I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . . .41

4.7 Output buffer impedance parameters. . . . . . . . . . .45

4.8 System modules timing . . . . . . . . . . . . . . . . . . . . .47

4.9 General-purpose media interface (GPMI) timing . .67

4.10 External peripheral interface parameters . . . . . . . .75

4.11 12-Bit A/D converter (ADC) . . . . . . . . . . . . . . . . . 112

Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 113

5.1 Boot mode configuration pins . . . . . . . . . . . . . . . . 113

5.2 Boot device interface allocation . . . . . . . . . . . . . . 114

Package information and contact assignments . . . . . . . 116

6.1 12 x 12 mm package information . . . . . . . . . . . . . 116

6.2 19 x 19 mm package information . . . . . . . . . . . . .134

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

NXP reserves the right to change the detail specifications as may be required to permit improvements in the design of

its products.

i.MX 7Dual introduction

The i.MX 7Dual family of processors is specifically useful for applications such as:

• Audio

• Connected devices

• Access control panels

• Human-machine interfaces (HMI)

• Portable medical and health care

• IP phones

• Smart appliances

• Point of Sale

• eReaders

• Wearables

• Home energy management systems

The features of the i.MX 7Dual family of processors include the following:

• ARM Cortex-A7 plus ARM Cortex-M4—Heterogeneous Multicore Processing architecture

enables the device to run an open operating system like Linux/Android on the Cortex-A7 core and

an RTOS like FreeRTOS™ on the Cortex-M4 core.

• Two ARM Cortex-A7 cores—The processor enhances the capabilities of portable, connected

applications by fulfilling the ever-increasing MIPS needs of operating systems and applications at

lowest power consumption levels per MHz.

• Multilevel memory system—The multilevel Cortex-A7 memory system is based on the L1

instruction and data caches, L2 cache, and internal and external memory. The processor supports

many types of external memory devices, including DDR3, DDR3L, LPDDR2 and LPDDR3, NOR

Flash, NAND Flash (MLC and SLC), QSPI Flash, and managed NAND, including eMMC rev.

• Power efficiency—Power management implemented throughout the IC enables features and

peripherals to consume minimum power in both active and various low-power modes.

• Multimedia—The multimedia performance is enhanced by a multilevel cache system, NEON™

MPE (Media Processor Engine) coprocessor, a programmable smart DMA (SDMA) controller.

• Up to two Gigabit Ethernet with AVB—10/100/1000 Mbps Ethernet controllers supporting IEEE

Std 1588 time synchronization.

• Electronic Paper Display Controller (EPDC)—The processor integrates an EPD controller that

supports E Ink color and monochrome panels with up to 2048 x 1536 resolution at 106 Hz refresh,

4096 x 4096 resolution at 20 Hz refresh, and 5-bit grayscale (32-levels per color channel).

• Human-machine interface (HMI)—i.MX 7Dual processor provides up to two separate display

interfaces (parallel display and two-lane MIPI-DSI), CMOS sensor interface (two-lane MIPI-CSI

and parallel).

• Interface flexibility—i.MX 7Dual processor supports connections to a variety of interfaces: two

high-speed USB on-the-go modules with PHY, High-Speed Inter-Chip USB, multiple expansion

card ports (high-speed MMC/SDIO host and other), two Gigabit Ethernet controllers with support

for Ethernet AVB, PCIe-II, two 12-bit ADCs with a total of 8 single-ended inputs, two CAN ports,

and a variety of other popular interfaces (such as UART, I

C, and I

S).

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

MCIMX7D2DVK12SD Related Products

	MCIMX7D2DVK12SD	MCIMX7D5EVM10SD	MCIMX7D7DVK10SD	MCIMX7D2DVM12SD	MCIMX7D3DVK10SD	MCIMX7D7DVM10SD
Description	Processor - Application-specific i.MX 7 series 32-bit MPU, Dual ARM Cortex-A7 core, 1.2GHz, MAPBGA 488	Processor - Application-specific i.MX 7Dual: Rev 1.3	Processor - Application-specific i.MX 7Dual: Rev 1.3	Processor - Application-specific i.MX 7 series 32-bit MPU, Dual ARM Cortex-A7 core, 1.2GHz, MAPBGA 541	Processor - Application-specific i.MX 7Dual: Rev 1.3	Processor - Application-specific i.MX 7Dual: Rev 1.3
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP	NXP	NXP
package instruction	TFBGA,	LFBGA,	TFBGA,	LFBGA,	TFBGA,	LFBGA,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
Other features	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE	24 MHZ NOMINAL CRYSTAL FREQ AVAILABLE
Address bus width	16	16	16	16	16	16
bit size	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES
External data bus width	32	32	32	32	32	32
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-B488	S-PBGA-B541	S-PBGA-B488	S-PBGA-B541	S-PBGA-B488	S-PBGA-B541
length	12 mm	19 mm	12 mm	19 mm	12 mm	19 mm
low power mode	YES	YES	YES	YES	YES	YES
Humidity sensitivity level	3	3	3	3	3	3
Number of terminals	488	541	488	541	488	541
Maximum operating temperature	85 °C	105 °C	95 °C	85 °C	95 °C	95 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	LFBGA	TFBGA	LFBGA	TFBGA	LFBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
Maximum seat height	1.1 mm	1.42 mm	1.1 mm	1.42 mm	1.1 mm	1.42 mm
speed	1200 MHz	1000 MHz	1000 MHz	1200 MHz	1000 MHz	1000 MHz
Maximum supply voltage	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V
Minimum supply voltage	1.2 V	1.045 V	1.045 V	1.2 V	1.045 V	1.045 V
Nominal supply voltage	1.225 V	1.1 V	1.1 V	1.225 V	1.1 V	1.1 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.4 mm	0.75 mm	0.4 mm	0.75 mm	0.4 mm	0.75 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40	40	40	40
width	12 mm	19 mm	12 mm	19 mm	12 mm	19 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC

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