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74AUP2G80GD,125

Description
Trigger Flip Flop D-Type Pos-Edge 2-ELM 8-Pin
Categorylogic    logic   
File Size289KB,22 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric Compare View All

74AUP2G80GD,125 Overview

Trigger Flip Flop D-Type Pos-Edge 2-ELM 8-Pin

74AUP2G80GD,125 Parametric

Parameter NameAttribute value
Brand NameNexperia
MakerNexperia
Parts packaging codeSON
package instruction3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT-996-2, XSON-8
Contacts8
Manufacturer packaging codeSOT996-2
Reach Compliance Codecompliant
seriesAUP/ULP/V
JESD-30 codeR-PDSO-N8
JESD-609 codee4
length3 mm
Load capacitance (CL)30 pF
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Sup70000000 Hz
MaximumI(ol)0.0017 A
Humidity sensitivity level1
Number of digits1
Number of functions2
Number of terminals8
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Encapsulate equivalent codeSOLCC8,.11,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, VERY THIN PROFILE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply1.2/3.3 V
Prop。Delay @ Nom-Sup27.2 ns
propagation delay (tpd)27.2 ns
Certification statusNot Qualified
Maximum seat height0.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.2 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
Trigger typePOSITIVE EDGE
width2 mm
minfmax510 MHz
74AUP2G80
Low-power dual D-type flip-flop; positive-edge trigger
Rev. 10 — 19 November 2018
Product data sheet
1. General description
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the
data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The
input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable
operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times
across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire V
CC
range
from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing a damaging backflow current through the device when it is powered
down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5 000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; I
CC
= 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74AUP2G80DC
-40 °C to +125 °C
Name
VSSOP8
Description
Version
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm

74AUP2G80GD,125 Related Products

74AUP2G80GD,125 74AUP2G80GM,125 74AUP2G80GN,115 74AUP2G80GF,115
Description Trigger Flip Flop D-Type Pos-Edge 2-ELM 8-Pin Trigger 1.8V DUAL LOW-POW TriggerLow-Power dual D-type flip-flop TriggerLow-Power dual D-type flip-flop
Brand Name Nexperia Nexperia Nexperia Nexperia
Maker Nexperia Nexperia Nexperia Nexperia
Parts packaging code SON QFN SON SON
package instruction 3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT-996-2, XSON-8 VQCCN, SON, VSON,
Contacts 8 8 8 8
Manufacturer packaging code SOT996-2 SOT902-2 SOT1116 SOT1089
Reach Compliance Code compliant compliant compliant compliant
series AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 code R-PDSO-N8 S-PQCC-N8 R-PDSO-N8 R-PDSO-N8
JESD-609 code e4 e4 e3 e3
length 3 mm 1.6 mm 1.2 mm 1.35 mm
Logic integrated circuit type D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
Humidity sensitivity level 1 1 1 1
Number of digits 1 1 1 1
Number of functions 2 2 2 2
Number of terminals 8 8 8 8
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C
Output polarity TRUE TRUE INVERTED INVERTED
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VSON VQCCN SON VSON
Package shape RECTANGULAR SQUARE RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE CHIP CARRIER, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 NOT SPECIFIED NOT SPECIFIED
propagation delay (tpd) 27.2 ns 27.2 ns 27.2 ns 27.2 ns
Maximum seat height 0.5 mm 0.5 mm 0.35 mm 0.5 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V 0.8 V 0.8 V
Nominal supply voltage (Vsup) 1.2 V 1.2 V 1.1 V 1.1 V
surface mount YES YES YES YES
technology CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface NICKEL PALLADIUM GOLD Nickel/Palladium/Gold (Ni/Pd/Au) Tin (Sn) Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm 0.3 mm 0.35 mm
Terminal location DUAL QUAD DUAL DUAL
Maximum time at peak reflow temperature 40 40 NOT SPECIFIED NOT SPECIFIED
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 2 mm 1.6 mm 1 mm 1 mm
minfmax 510 MHz 510 MHz 510 MHz 510 MHz
Samacsys Description - 74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger@en-us 74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger@en-us 74AUP2G80 - Low-power dual D-type flip-flop; positive-edge trigger@en-us
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