1:2 Differential-to-LVPECL
Buffer/Divider
Data Sheet
8S89874
General Description
The 8S89874 is a high speed 1:2 Differential-to- LVPECL Buffer/
Divider. The 8S89874 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output
divider, which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal termination
resistors, allowing it to interface with several differential signal types
while minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package, making
it ideal for use on space-constrained boards.
Features
•
•
•
•
•
•
•
•
•
•
•
Two LVPECL/ECL output pairs
Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,
÷16
IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
Output frequency: 2GHz (maximum)
Output skew: 15ps (maximum)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.20ps (typical)
LVPECL supply voltage range: 2.375V to 3.63V
ECL supply voltage range: -3.63V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
S2
Pullup
Pin Assignment
V
CC
14
nRESET
Pullup
Enable
FF
Enable
MUX
Q0
0
nQ0
Q0
nQ0
Q1
Q1
nQ1
1
2
3
4
16
15
V
EE
13
12
11
S0
S1
IN
V
T
V
REF_AC
nIN
8S89874
1
IN
50Ω
8XXXXXX
5
6
7
8
10
9
V
T
nIN
50Ω
S0
Pullup
S1
Pullup
V
REF_AC
Decoder
16-pin, 3mm x 3mm VFQFN Package
©2016 Integrated Device Technology, Inc
1
Revision B February 9, 2016
nRESET
V
CC
S2
nc
00
01
10
11
÷2
÷4
÷8
÷16
nQ1
8S89874 Data Sheet
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 15, 16
6
7, 14
8
9
10
11
12
13
Name
Q0, nQ0
Q1, nQ1
S2, S1, S0
nc
V
cc
nRESET
nIN
V
REF_AC
V
T
IN
V
EE
Type
Output
Output
Input
Unused
Power
Input
Input
Output
Input
Input
Power
Pullup
Pullup
Description
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Select pins. LVCMOS/LVTTL interface levels.
No connect.
Positive supply pins.
When LOW, resets the divider. Pulled HIGH when left unconnected. Input threshold
is V
CC
/2. Includes a 37k
pullup resistor. LVTTL/LVCMOS interface levels.
Inverting differential LVPECL clock input. R
T
= 50
termination to V
T
.
Reference voltage for AC-coupled applications.
Termination input.
Non-inverting LVPECL differential clock input. R
T
= 50
termination to V
T
.
Negative supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
k
©2016 Integrated Device Technology, Inc
2
Revision B February 9, 2016
8S89874 Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs
nRESET
0
1
Selected Source
IN/nIN
IN/nIN
Q0, Q1
Disabled; LOW
Enabled
Outputs
nQ0, nQ1
Disabled; HIGH
Enabled
V
CC
/2
nRESET
IN
nIN
t
RR
V
IN
V
IN
Swing
t
PD
V
OUT
Swing
nQx
Qx
Figure 1. nRESET Timing Diagram
Table 3B. Truth Table
Inputs
nRESET
1
1
1
1
1
0
0
S2
0
1
1
1
1
1
0
S1
X
0
0
1
1
X
X
S0
X
0
1
0
1
X
X
Outputs
Reference Clock ÷1 (pass through)
Reference Clock ÷2
Reference Clock ÷4
Reference Clock ÷8
Reference Clock ÷16
Q = LOW, nQ = HIGH; Clock Disabled
Q = LOW, nQ = HIGH; Clock Disabled
©2016 Integrated Device Technology, Inc
3
Revision B February 9, 2016
8S89874 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
V
REF_AC
Input Sink/Source, I
REF_AC
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
-0.5V to + 4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±50mA
±100mA
±2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 10% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.63
45
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 10% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
CC
= V
IN
= 3.63V or 2.625V
V
CC
= 3.63V or 2.625V, V
IN
= 0V
-150
Test Conditions
Minimum
2.2
0
Typical
Maximum
V
CC
+ 0.3
0.8
10
Units
V
V
µA
µA
©2016 Integrated Device Technology, Inc
4
Revision B February 9, 2016
8S89874 Data Sheet
Table 4C. Differential DC Characteristics,
V
CC
= 3.3V ± 10% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
I
IN
V
REF_AC
Parameter
Differential Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input Voltage Swing
Input Current; NOTE 1
Bias Voltage
(IN, nIN)
V
CC
– 1.45
V
CC
– 1.37
(IN, nIN)
(IN, nIN)
(IN, nIN)
Test Conditions
Minimum
40
1.2
0
0.15
0.3
35
V
CC
– 1.32
Typical
50
Maximum
60
V
CC
V
IH
– 0.15
1.2
Units
V
V
V
V
mA
V
NOTE 1: Guaranteed by design.
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 10% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.175
V
CC
– 2.0
0.6
1.2
Typical
Maximum
V
CC
– 0.82
V
CC
– 1.575
1.0
2.0
Units
V
V
V
V
NOTE: Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
©2016 Integrated Device Technology, Inc
5
Revision B February 9, 2016
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