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dsPIC33FJ128GP206A-E/MR

Description
Digital Signal Processor and Controller-DSP, DSC 16 Bit MCU/DSP 64LD 40MIPS 128KB FLASH
Categorysemiconductor    The embedded processor and controller    Digital signal processor and controller - DSP, DSC   
File Size3MB,363 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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dsPIC33FJ128GP206A-E/MR Overview

Digital Signal Processor and Controller-DSP, DSC 16 Bit MCU/DSP 64LD 40MIPS 128KB FLASH

dsPIC33FJ128GP206A-E/MR Parametric

Parameter NameAttribute value
MakerMicrochip
Product CategoryDigital Signal Processors and Controllers - DSP, DSC
Package/boxQFN-64
seriesdsPIC33FJxxxGPx06A
productDSCs
coredsPIC33FJ
maximum clock frequency40 MHz
Program memory size128 kB
Data RAM size8 kB
Working power voltage3 V to 3.6 V
Minimum operating temperature- 40 C
Maximum operating temperature+ 125 C
EncapsulationTube
high0.88 mm
length9 mm
Program memory typeFlash
width9 mm
Interface TypeI2C/SPI/UART
Number of input/output terminals53 I/O
Data bus width16 bit
Number of timers/counters9 Timer
Processor seriesdsPIC33F
Factory packaging quantity40
Supply voltage - min.3 V
dsPIC33FJXXXGPX06A/X08A/X10A
16-bit Digital Signal Controllers (up to 256 KB Flash and
30 KB SRAM) with Advanced Analog
Operating Conditions
• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS
• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS
Timers/Output Compare/Input Capture
• Up to nine 16-bit timers/counters. Can pair up to
make four 32-bit timers.
• Eight Output Compare modules configurable as
timers/counters
• Eight Input Capture modules
Core: 16-bit dsPIC33F CPU
Code-efficient (C and Assembly) architecture
Two 40-bit wide accumulators
Single-cycle (MAC/MPY) with dual data fetch
Single-cycle mixed-sign MUL plus hardware
divide
Communication Interfaces
• Two UART modules (10 Mbps)
- With support for LIN 2.0 protocols and IrDA
®
• Two 4-wire SPI modules (15 Mbps)
• Up to two I
2
C™ modules (up to 1 Mbaud) with
SMBus support
• Up to two Enhanced CAN (ECAN) modules
(1 Mbaud) with 2.0B support
• Data Converter Interface (DCI) module with I
2
S
codec support
Clock Management
±2% internal oscillator
Programmable PLLs and oscillator clock sources
Fail-Safe Clock Monitor (FSCM)
Independent Watchdog Timer (WDT)
Fast wake-up and start-up
Power Management
• Low-power management modes (Sleep, Idle,
Doze)
• Integrated Power-on Reset and Brown-out Reset
• 2.1 mA/MHz dynamic current (typical)
• 50
μA
I
PD
current (typical)
Input/Output
• Sink/Source up to 10 mA (pin specific) for stan-
dard V
OH
/V
OL
, up to 16 mA (pin specific) for
non-standard V
OH1
• 5V-tolerant pins
• Selectable open drain, pull-ups, and pull-downs
• Up to 5 mA overvoltage clamp current
• External interrupts on all I/O pins
Advanced Analog Features
• Two ADC modules:
- Configurable as 10-bit, 1.1 Msps with four
S&H or 12-bit, 500 ksps with one S&H
- 18 analog inputs on 64-pin devices and up to
32 analog inputs on 100-pin devices
• Flexible and independent ADC trigger sources
Qualification and Class B Support
• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)
• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)
• Class B Safety Library, IEC 60730
Debugger Development Support
In-circuit and in-application programming
Two program and two complex data breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Trace and run-time watch
Packages
Type
QFN
TQFP
64
0.50
53
10x10x1
TQFP
80
0.50
69
12x12x1
TQFP
100
0.40
85
14x14x1
Pin Count
64
Contact Lead/Pitch
0.50
I/O Pins
53
Dimensions
9x9x0.9
Note:
All dimensions are in millimeters (mm) unless specified.
2009-2012 Microchip Technology Inc.
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