HEF40240B
Octal inverting buffers with 3-state outputs
Rev. 5 — 15 November 2011
Product data sheet
1. General description
The HEF40240B is an octal inverting buffer with 3-state outputs. It features output stages
with high current output capability suitable for driving highly capacitive loads.
The 3-state outputs are controlled by the output enable inputs nOE. A HIGH on nOE
causes the outputs to assume a high-impedance OFF-state. The device also features
hysteresis on all inputs to improve noise immunity. Schmitt-trigger action makes the inputs
highly tolerant to slow input rise and fall times.
The HEF40240B is pin and functionally compatible with the TTL ‘240’ device.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow input rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF40240BP
HEF40240BT
Package
Name
DIP20
SO20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT146-1
SOT163-1
NXP Semiconductors
HEF40240B
Octal inverting buffers with 3-state outputs
4. Functional diagram
1A0
2
18
1Y0
1A1
4
16
1Y1
1A2
6
14
1Y2
1A3
1OE
2A0
8
1
11
12
1Y3
9
2Y0
nA0
nY0
2A1
13
7
2Y1
nA1
nY1
2A2
15
5
2Y2
nA2
nY2
2A3
2OE
17
19
3
2Y3
nA3
nY3
001aal325
nOE
001aal373
Fig 1.
Functional diagram
Fig 2.
Logic diagram
5. Pinning information
5.1 Pinning
HEF40240B
1OE
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
1
2
3
4
5
6
7
8
9
20 V
DD
19 2OE
HEF40240B
18 1Y0
17 2A3
16 1Y1
15 2A2
14 1Y2
13 2A1
12 1Y3
11 2A0
001aal326
1OE
1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0
1
2
3
4
5
6
7
8
9
20 V
DD
19 2OE
18 1Y0
17 2A3
16 1Y1
15 2A2
14 1Y2
13 2A1
12 1Y3
11 2A0
001aal372
V
SS
10
V
SS
10
Fig 3.
Pin configuration DIP20
Fig 4.
Pin configuration SO20
HEF40240B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 15 November 2011
2 of 15
NXP Semiconductors
HEF40240B
Octal inverting buffers with 3-state outputs
5.2 Pin description
Table 2.
Symbol
1OE
1A0, 1A1, 1A2, 1A3
V
SS
2Y0, 2Y1, 2Y2, 2Y3
2A0, 2A1, 2A2, 2A3
V
DD
1Y0, 1Y1, 1Y2, 1Y3
2OE
Pin description
Pin
1
2, 4, 6, 8
10
9, 7, 5, 3
11, 13, 15, 17
20
18, 16, 14, 12
19
Description
output enable input (active LOW)
data input
ground (0 V)
data output
data input
supply voltage
data output
output enable input (active LOW)
6. Functional description
Table 3.
Inputs
nAn
H
L
X
[1]
Function table
[1]
Output
nOE
L
L
H
nYn
L
H
Z
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I
I
O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input leakage current
output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
=
40 C
to +85
C
DIP20 package
SO20 package
P
[1]
[2]
[3]
[2]
[3]
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
into any input
sink or source current
to any supply terminal
[1]
Min
0.5
-
0.5
-
-
-
-
65
40
-
-
-
Max
+18
10
V
DD
+ 0.5
10
10
25
100
+150
+85
750
500
100
Unit
V
mA
V
mA
mA
mA
mA
C
C
mW
mW
mW
power dissipation
See
Figure 6.
per output
For DIP20 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO20 package: P
tot
derates linearly with 8 mW/K above 70
C.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
HEF40240B
Product data sheet
Rev. 5 — 15 November 2011
3 of 15
NXP Semiconductors
HEF40240B
Octal inverting buffers with 3-state outputs
V
DD
P
0
N
V
SS
001aal328
Fig 5.
Schematic diagram of a buffer output stage
0
I
OH
(mA)
−25
V
DD
= 5 V
(1)
001aal327
−50
10 V
(2)
15 V
−75
−100
−2.0
−1.5
−1.0
−0.5
0
(V
DD
−
V
OH
) (V)
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar NPN transistor conducting.
Fig 6.
Typical output source current characteristic
8. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+85
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
HEF40240B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 15 November 2011
4 of 15
NXP Semiconductors
HEF40240B
Octal inverting buffers with 3-state outputs
9. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level input voltage
I
O
< 1
A
5V
10 V
15 V
V
H
hysteresis voltage
for any input
5V
10 V
15 V
V
OH
HIGH-level output voltage
I
O
< 1
A
5V
10 V
15 V
V
OL
LOW-level output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level output current
V
O
= 3.6 V
V
O
= 8.4 V
V
O
= 13.2 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage current
supply current
I
O
= 0 A
5V
10 V
15 V
5V
10 V
15 V
5V
10 V
15 V
15 V
5V
10 V
15 V
I
OZ
C
I
OFF-state output current
input capacitance
15 V
-
T
amb
=
40 C
Min
3.5
7.0
11.0
-
-
-
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
-
-
2.9
9.5
30.0
-
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
-
-
-
0.05
0.05
0.05
9.3
14.4
19.5
0.75
1.85
14.5
-
-
-
0.3
4
8
16
1.6
-
T
amb
= +25
C
Min
3.5
7.0
11.0
-
-
-
-
-
-
4.95
9.95
14.95
-
-
-
24.0
46.0
62.0
1.2
3.0
50.0
2.3
7.6
25.0
-
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
220.0
250.0
320.0
-
-
-
0.05
0.05
0.05
10.0
15.0
20.0
0.6
1.5
15.0
5.4
17.0
45.0
0.3
4
8
16
1.6
7.5
T
amb
= +85
C
Unit
Min
3.5
7.0
11.0
-
-
-
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
-
-
1.75
5.50
19.0
-
-
-
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
-
-
-
0.05
0.05
0.05
V
V
V
V
V
V
mV
mV
mV
V
V
V
V
V
V
10.7
mA
15.0
mA
19.8
mA
0.45
mA
1.1
-
-
-
1.0
30
60
120
12
-
mA
mA
mA
mA
A
A
A
A
A
pF
15.5
mA
HEF40240B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 15 November 2011
5 of 15
京公网安备 11010802033920号
EEWORLD
