MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
High−Performance Silicon−Gate CMOS
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The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flip−flops, but when Output Enable is high, all device outputs
are forced to the high−impedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
•
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
•
These Devices are Pb−Free and are RoHS Compliant
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
3
4
5
6
7
8
9
11
1
PIN 20 = V
CC
PIN 10 = GND
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NON-
INVERTING
OUTPUTS
MARKING DIAGRAMS
20
HCT574A
AWLYYWWG
1
SOIC−20
1
TSSOP−20
20
HCT
574A
ALYWG
G
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
OE
L
L
L
H
Clock
D
H
L
X
X
Output
Q
H
L
No Change
Z
Figure 1. Logic Diagram
L,H,
X
X = don’t care
Z = high impedance
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 11
Publication Order Number:
MC74HCT574A/D
MC74HCT574A
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Design Criteria
Value
71.5
1.5
5.0
Units
ea
ns
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
mW
pJ
0.0075
*Equivalent to a two−input NAND gate.
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
–0.5 to +7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
±20
±35
±75
500
–65 to +150
260
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 secs
(SOIC Package)
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: – 7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 2)
Min
4.5
0
–55
0
Max
5.5
V
CC
+125
500
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MC74HCT574A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
6.0 mA
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
6.0 mA
I
in
I
CC
I
OZ
DI
CC
Maximum Input Leakage Current
Maximum Quiescent Supply Current
(per Package)
Maximum Three−State Leakage
Current
Additional Quiescent Supply Current
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
V
in
= V
IL
or V
IH
(Note 1)
V
out
= V
CC
or GND
V
in
= 2.4 V, Any One Input
V
in
= V
CC
or GND, Other Inputs
l
out
= 0
mA
V
CC
V
4.5
5.5
4.5
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
5.5
–55 to
25_C
2.0
2.0
0.8
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
4.0
−0.5
≥
–55_C
5.5
2.9
≤
85_C
2.0
2.0
0.8
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
40
–5.0
≤
125_C
2.0
2.0
0.8
0.8
4.4
5.4
V
3.7
0.1
0.1
0.4
±1.0
160
mA
–10
mA
mA
Unit
V
V
25_C to 125_C
2.4
mA
1. Output in high−impedance state.
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ÎÎ
Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Î
Guaranteed Limit
v
85_C
24
38
35
35
15
Symbol
f
MAX
Parameter
– 55 to
25_C
30
30
28
28
12
v
125_C
20
45
42
42
18
Unit
Maximum Clock Frequency (50% Duty Cycle) (Figures 2 and 5)
Maximum Propagation Delay, Clock to Q
(Figures 2 and 5)
MHz
ns
ns
ns
ns
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
t
PZH
,
t
PZL
t
TLH
,
t
THL
C
in
Maximum Propagation Delay Time, Output Enable to Q
(Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 2, 3 and 5)
Maximum Input Capacitance
10
10
10
pF
Typical @ 25°C, V
CC
= 5.0 V
58
C
PD
Power Dissipation Capacitance (Per Flip−Flop)*
pF
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0 V
±10%,
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
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Î
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Î
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Î
Î
Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î Î Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
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Î
Î
Î
Î
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TIMING REQUIREMENTS
(V
CC
= 5.0 V
±10%,
C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
v
85_C
– 55 to 25_C
v
125_C
Symbol
t
su
t
h
t
w
Parameter
Figure
4
4
2
2
Min
10
15
5.0
Max
Min
13
19
5.0
Max
Min
15
22
5.0
Max
Unit
ns
ns
ns
ns
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
Minimum Pulse Width, Clock
t
r
, If
Maximum Input Rise and Fall Times
500
500
500
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f
+ I
CC
V
CC
.
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3
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
CLOCK
11
C
D
Q
C
D
Q
C
D
Q
C
D
Q
C
D
Q
C
D
Q
C
D
Q
C
D
Q
ENABLE
OUTPUT
1
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SWITCHING WAVEFORMS
t
r
CLOCK
2.7 V
1.3 V
0.3 V
t
w
1/f
max
t
PLH
Q
90%
1.3 V
10%
t
TLH
t
THL
t
PHL
Q
t
f
3.0 V
GND
OUTPUT
ENABLE
1.3 V
GND
t
PZL
1.3 V
t
PZH
Q
1.3 V
t
PHZ
10%
90%
t
PLZ
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
3.0 V
Figure 2.
Figure 3.
TEST POINT
VALID
3.0 V
1.3 V
DATA
GND
t
su
t
h
3.0 V
1.3 V
CLOCK
GND
DEVICE
UNDER
TEST
OUTPUT
C
L
*
*Includes all probe and jig capacitance
Figure 4.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
Figure 5. Test Circuit
C
L
*
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
*Includes all probe and jig capacitance
Figure 6. Test Circuit
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4
MC74HCT574A
ORDERING INFORMATION
Device
MC74HCT574ADWG
MC74HCT574ADWR2G
MC74HCT574ADTR2G
Package
SOIC−20 WIDE
(Pb−Free)
SOIC−20 WIDE
(Pb−Free)
TSSOP−20
(Pb−Free)
Shipping
†
38 Units / Rail
1000 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
Embedded System
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