Register Map: Section
6.2
ZL30260-ZL30263
1-APLL, 6- or 10-Output Any-to-Any Clock
Multiplier and Frequency Synthesizer
Data Sheet
October 2018
Features
•
Four Flexible Input Clocks
•
One crystal/CMOS input
•
Two differential/CMOS inputs
•
One single-ended/CMOS input
•
Any input frequency from 9.72MHz to 1.25GHz
(300MHz max for CMOS)
•
Activity monitors, automatic or manual switching
•
Glitchless clock switching by pin or register
•
6 or 10 Any-Frequency, Any-Format Outputs
•
Any output frequency from 1Hz to 1045MHz
•
High-resolution frac-N APLL with 0ppm error
•
The APLL has a fractional divider and an
integer divider to make two independent
frequency families
•
Output jitter from integer multiply and dividers
as low as 0.17ps RMS (12kHz-20MHz)
•
Output jitter from fractional dividers is typically
< 1ps RMS, many frequencies <0.5ps RMS
•
Each output has an independent divider
•
Each output configurable as LVDS, LVPECL,
HCSL, 2xCMOS or HSTL
•
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
•
Multiple output supply voltage banks with
CMOS output voltages from 1.5V to 3.3V
•
Precise output alignment circuitry and per-
output phase adjustment
IC1P, IC1N
IC2P, IC2N
IC3P
XA
XB
DIV
DIV
DIV
DIV
x2
Ordering Information
ZL30260LDG1
ZL30260LDF1
ZL30261LDG1
ZL30261LDF1
ZL30262LDG1
ZL30262LDF1
ZL30263LDG1
ZL30263LDF1
ext. EEPROM
ext. EEPROM
int. EEPROM
int. EEPROM
ext. EEPROM
ext. EEPROM
int. EEPROM
int. EEPROM
6 Outputs
6 Outputs
6 Outputs
6 Outputs
10 Outputs
10 Outputs
10 Outputs
10 Outputs
Trays
Tape and Reel
Trays
Tape and Reel
Trays
Tape and Reel
Trays
Tape and Reel
Matte Tin
Package size: 8 x 8 mm, 56 Pin QFN
-40
C to +85
C
•
Per-output enable/disable and glitchless
start/stop (stop high or low)
•
General Features
•
Automatic self-configuration at power-up from
external (ZL30260 or 2) or internal (ZL30261 or 3)
EEPROM; up to 8 configurations pin-selectable
•
External feedback for zero-delay applications
•
Numerically controlled oscillator mode
•
Spread-spectrum modulation mode
•
Generates PCIe 1, 2, 3, 4 compliant clocks
•
Easy-to-configure design requires no external
VCXO or loop filter components
•
SPI or I
2
C processor Interface
•
Core supply voltage options: 2.5V only, 3.3V
only, 1.8V+2.5V or 1.8V+3.3V
•
Space-saving 8x8mm QFN56 (0.5mm pitch)
Applications
•
Frequency conversion and frequency synthesis in
a wide variety of equipment types
DIV1
DIV2
Frac DIV
bypass
Int DIV
x2
VDDOA
OC1P, OC1N
OC2P, OC2N
VDDOB
OC3P, OC3N
VDDOC
OC4P, OC4N
OC5P, OC5N
VDDOD
OC6P, OC6N
OC7P, OC7N
VDDOE
OC8P, OC8N
VDDOF
OC9P, OC9N
OC10P, OC10N
APLL
Fractional-N
Figure 5
xtal
driver
DIV3
DIV4
DIV5
DIV6
Path 2
RSTN
AC0/GPIO0
AC1/GPIO1
AC2/GPIO2
TEST/GPIO3
IF0/CSN
IF1/MISO
SCL/SCLK
SDA/MOSI
10-output
devices only
(SPI or I2C Serial)
and GPIO Pins
Microprocessor
Port
DIV7
DIV8
DIV9
DIV10
Figure 1 - Functional Block Diagram
1
Microsemi Confidential
Copyright 2018. Microsemi Corporation. All Rights Reserved.
ZL30260-ZL30263
Data Sheet
Table of Contents
1.
2.
2.1
2.2
2.3
2.4
2.5
3.
4.
5.
5.1
5.2
5.3
APPLICATION EXAMPLE ............................................................................................................ 5
DETAILED FEATURES ................................................................................................................. 5
I
NPUT
C
LOCK
F
EATURES
.............................................................................................................. 5
APLL F
EATURES
.......................................................................................................................... 5
O
UTPUT
C
LOCK
F
EATURES
........................................................................................................... 5
G
ENERAL
F
EATURES
.................................................................................................................... 5
E
VALUATION
S
OFTWARE
............................................................................................................... 6
PIN DIAGRAM ............................................................................................................................... 6
PIN DESCRIPTIONS ..................................................................................................................... 7
FUNCTIONAL DESCRIPTION ...................................................................................................... 9
D
EVICE
I
DENTIFICATION
................................................................................................................ 9
P
IN
-C
ONTROLLED
A
UTOMATIC
C
ONFIGURATION AT
R
ESET
............................................................. 9
ZL30260 and ZL30262—Internal ROM, External or No EEPROM ...................................................... 10
ZL30261 and ZL30263—Internal EEPROM ........................................................................................ 10
External Oscillator ................................................................................................................................ 11
External Crystal and On-Chip Driver Circuit ........................................................................................ 11
Clock Doublers ..................................................................................................................................... 12
Ring Oscillator (for Auto-Configuration) ............................................................................................... 13
5.2.1
5.2.2
5.3.1
5.3.2
5.3.3
5.3.4
L
OCAL
O
SCILLATOR OR
C
RYSTAL
................................................................................................ 11
5.4
5.5
I
NPUT
S
IGNAL
F
ORMAT
C
ONFIGURATION
...................................................................................... 13
APLL C
ONFIGURATION
............................................................................................................... 13
5.5.1
APLL Input Frequency ......................................................................................................................... 13
5.5.2
APLL Input Monitors ............................................................................................................................. 13
5.5.3
APLL Input Selection ............................................................................................................................ 13
5.5.4
APLL Output Frequency....................................................................................................................... 14
5.5.5
Fractional Output Divider ..................................................................................................................... 15
5.5.6
Numerically Controlled Oscillator (NCO) Mode ................................................................................... 16
5.5.6.1 Using the APLL’s Feedback Divider ................................................................................................ 16
5.5.6.2 Using the Fractional Output Divider ................................................................................................. 16
5.5.7
Frequency Increment and Decrement ................................................................................................. 17
5.5.8
Spread-Spectrum Modulation Mode .................................................................................................... 17
5.5.8.1 Using the APLL’s Feedback Divider ................................................................................................ 17
5.5.8.2 Using the Fractional Output Divider ................................................................................................. 18
5.5.9
APLL Phase Adjustment ...................................................................................................................... 19
5.6
O
UTPUT
C
LOCK
C
ONFIGURATION
................................................................................................ 19
Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 19
Output Frequency Configuration .......................................................................................................... 20
Output Duty Cycle Adjustment ............................................................................................................. 21
Output Phase Adjustment .................................................................................................................... 21
Output-to-Output Phase Alignment ...................................................................................................... 21
Output-to-Input Phase Alignment ......................................................................................................... 21
Output Clock Start and Stop ................................................................................................................ 21
SPI Slave ............................................................................................................................................. 22
SPI Master (ZL30260 and ZL30262 Only) ........................................................................................... 24
I
2
C Slave .............................................................................................................................................. 25
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.7
M
ICROPROCESSOR
I
NTERFACE
................................................................................................... 22
5.7.1
5.7.2
5.7.3
5.8
5.9
I
NTERRUPT
L
OGIC
...................................................................................................................... 27
R
ESET
L
OGIC
............................................................................................................................. 28
Design Considerations for Using an External RC Reset Circuit .......................................................... 28
5.9.1
2
Microsemi Confidential
ZL30260-ZL30263
5.10
5.11
5.11.1
5.11.2
5.11.3
Data Sheet
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.......................................................................................... 28
A
UTO
-C
ONFIGURATION FROM
EEPROM
OR
ROM .................................................................... 28
Generating Device Configurations ....................................................................................................... 29
Direct EEPROM Write Mode (ZL30261 and ZL30263 Only) ............................................................... 29
Holding Other Devices in Reset During Auto-Configuration ................................................................ 29
5.12
5.13
5.14
5.15
6.
6.1
C
ONFIGURATION
S
EQUENCE
.................................................................................................... 29
P
OWER
S
UPPLY
D
ECOUPLING AND
L
AYOUT
R
ECOMMENDATIONS
............................................... 29
C
HOOSING
A
MONG
C
ORE
P
OWER
S
UPPLY
O
PTIONS
................................................................. 29
P
ATH
2 S
IGNAL
S
ELECTION
...................................................................................................... 30
R
EGISTER
T
YPES
....................................................................................................................... 30
Status Bits ............................................................................................................................................ 30
Configuration Fields ............................................................................................................................. 31
Multiregister Fields ............................................................................................................................... 31
Bank-Switched Registers (ZL30261 and ZL30263 Only) .................................................................... 31
REGISTER DESCRIPTIONS ....................................................................................................... 30
6.1.1
6.1.2
6.1.3
6.1.4
6.2
6.3
R
EGISTER
M
AP
.......................................................................................................................... 31
R
EGISTER
D
EFINITIONS
.............................................................................................................. 34
Global Configuration Registers ............................................................................................................ 34
Status Registers ................................................................................................................................... 43
APLL Configuration Registers .............................................................................................................. 52
Path 2 Configuration Registers ............................................................................................................ 66
Output Clock Configuration Registers .................................................................................................. 68
Input Clock Configuration Registers .................................................................................................... 75
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
7.
8.
9.
10.
11.
ELECTRICAL CHARACTERISTICS ........................................................................................... 77
PACKAGE AND THERMAL INFORMATION .............................................................................. 89
MECHANICAL DRAWING .......................................................................................................... 90
ACRONYMS AND ABBREVIATIONS ......................................................................................... 91
DATA SHEET REVISION HISTORY ........................................................................................... 92
3
Microsemi Confidential
ZL30260-ZL30263
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram ........................................................................................................................... 1
Figure 2 - Application Example: PCIe and Ethernet Clocks for Server Application .................................................... 5
Figure 3 - Pin Diagram ................................................................................................................................................. 6
Figure 4 - Crystal Equivalent Circuit / Recommended Crystal Circuit ....................................................................... 11
Figure 5 - APLL Block Diagram ................................................................................................................................. 14
Figure 6 - SPI Read Transaction Functional Timing.................................................................................................. 23
Figure 7 - SPI Write Enable Transaction Functional Timing (ZL30261 and ZL30263 Only) ..................................... 24
Figure 8 - SPI Write Transaction Functional Timing .................................................................................................. 24
Figure 9 - I
2
C Read Transaction Functional Timing .................................................................................................. 26
Figure 10 - I
2
C Register Write Transaction Functional Timing .................................................................................. 26
Figure 11 - I
2
C EEPROM Write Transaction Functional Timing (ZL30261 and ZL30263 Only) ............................... 26
Figure 12 - I
2
C EEPROM Read Status Transaction Functional Timing (ZL30261 and ZL30263 Only) .................... 26
Figure 13 - Interrupt Structure ................................................................................................................................... 27
Figure 14 - Electrical Characteristics: Clock Inputs ................................................................................................... 79
Figure 15 - Example External Components for Differential Input Signals ................................................................. 80
Figure 16 - Electrical Characteristics: Differential Clock Outputs .............................................................................. 80
Figure 17 - Example External Components for Output Signals ................................................................................. 82
Figure 18 - SPI Slave Interface Timing ...................................................................................................................... 85
Figure 19 - SPI Master Interface Timing .................................................................................................................... 87
Figure 20 - I
2
C Slave Interface Timing ....................................................................................................................... 88
List of Tables
Table 1 - Pin Descriptions ............................................................................................................................................ 7
Table 2 - Crystal Selection Parameters ..................................................................................................................... 12
Table 3 - SPI Commands .......................................................................................................................................... 22
Table 4 - Register Map .............................................................................................................................................. 31
Table 5 - Recommended DC Operating Conditions .................................................................................................. 77
Table 6 - Electrical Characteristics: Supply Currents ................................................................................................ 77
Table 7 - Electrical Characteristics: Non-Clock CMOS Pins ..................................................................................... 78
Table 8 - Electrical Characteristics: XA Clock Input .................................................................................................. 79
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N ......................................................................................... 79
Table 10 - Electrical Characteristics: LVDS Clock Outputs ....................................................................................... 80
Table 11 - Electrical Characteristics: LVPECL Clock Outputs .................................................................................. 81
Table 12 - Electrical Characteristics: HCSL Clock Outputs ....................................................................................... 81
Table 13 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 81
Table 14 - Electrical Characteristics: APLL Frequencies .......................................................................................... 82
Table 15 - Electrical Characteristics: Jitter and Skew Specifications ........................................................................ 82
Table 16 - Electrical Characteristics: Typical Output Phase Jitter from the APLL Integer Divider ............................ 83
Table 17 - Electrical Characteristics: Clock Buffer (APLL Bypass Path and Path 2) ................................................ 84
Table 18 - Electrical Characteristics: Typical Input-to-Output Clock Delay Through APLL ....................................... 84
Table 19 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers ................................................ 85
Table 20 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM .............................................. 86
Table 21 - Electrical Characteristics: SPI Master Interface Timing (ZL30260 and ZL30262 Only) ........................... 87
Table 22 - Electrical Characteristics: I
2
C Slave Interface Timing .............................................................................. 88
Table 23 - 8x8mm QFN Package Thermal Properties .............................................................................................. 89
4
Microsemi Confidential
ZL30260-ZL30263
1. Application Example
4x 156.25MHz differential
2x 100MHz differential
100MHz CMOS
2x 25MHz differential
25MHz CMOS
Data Sheet
XO
ZL30263
Figure 2 - Application Example: PCIe and Ethernet Clocks for Server Application
2. Detailed Features
2.1
Input Clock Features
•
•
•
•
Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS
Input clocks can be any frequency from 9.72MHz to 1250MHz (differential) or 300MHz (single-ended)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Activity monitor and glitchless input switching
Very high-resolution fractional (i.e. non-integer) frequency multiplication
Any-to-any frequency conversion with 0ppm error
Two APLL output dividers: one integer divider (4 to 15 plus half divides 4.5 to 7.5) and one fractional
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
Bypass mode supports system testing
Six (ZL30260 or ZL30261) or ten (ZL30262 or ZL30263) low-jitter output clocks
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1045MHz (250MHz max for HCSL, CMOS and HSTL)
Output jitter from integer multiply and integer dividers as low as 0.17ps RMS (12kHz to 20MHz)
Output jitter from fractional dividers is typically <1ps RMS, many frequencies <0.5ps RMS (12kHz to
20MHz)
In CMOS mode, the OCxP and OCxN pins can be different divisors (Example 1: OC3P 125MHz, OC3N
25MHz; Example 2: OC3P 25MHz, OC3N 1Hz/1PPS)
Outputs directly interface (DC coupled) with LVDS, LVPECL, HSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe-compliant clocks (PCIe 1, 2, 3 and 4)
Sophisticated output-to-output phase alignment
Per-output phase adjustment
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
SPI or I
2
C serial microprocessor interface
Automatic self-configuration at power-up; pin control to specify one of 8 stored configurations
ZL30260 and ZL30262: preset configurations in ROM or user configurations in external EEPROM
ZL30261 and ZL30263: user configurations in internal EEPROM
Numerically controlled oscillator (NCO) mode allows system software to steer DPLL frequency with
resolution better than 0.01ppb (1ppt can be achieved with fractional output divider value >14.56)
Spread-spectrum modulation mode (meets PCI Express requirements)
Zero-delay buffer configuration using an external feedback path
Four general-purpose I/O pins each with many possible status and control options
Reference can be fundamental-mode crystal, low-cost XO or clock signal from elsewhere in the system
2.2
APLL Features
•
•
•
•
•
2.3
Output Clock Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.4
General Features
•
•
•
•
•
•
•
5
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Analog electronics
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