AD9550/PCBZ datasheet, PDF - EEWORLD Datasheet

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AD9550/PCBZ: DescriptionClock and Timer Development Tools AD9550 Eval Brd; CategoryEmbedded solution Engineering tools Analog and digital IC development tools The clock and timer development tools; File Size383KB，21 Pages; ManufacturerADI; Websitehttps://www.analog.com; Environmental Compliance

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AD9550/PCBZ Overview

Clock and Timer Development Tools AD9550 Eval Brd

AD9550/PCBZ Parametric

Parameter Name	Attribute value
Maker	ADI
Product Category	Clock and timer development tools
product	Evaluation Boards
type	Clock Translators
Tools for assessment	AD9550
frequency	200 MHz, 810 MHz
Encapsulation	Bulk
series	AD9550
Interface Type	Pin Select
Working power voltage	3.3 V
Factory packaging quantity	1
unit weight	1 kg

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Integer-N Clock Translator

for Wireline Communications

AD9550

FEATURES

Converts preset standard input frequencies to standard

output frequencies

Input frequencies from 8 kHz to 200 MHz

Output frequencies up to 810 MHz LVPECL and LVDS

(200 MHz CMOS)

Preset pin-programmable frequency translation ratios

On-chip VCO

Single-ended CMOS reference input

Two output clocks (independently programmable as LVDS,

LVPECL, or CMOS)

Single supply (3.3 V)

Very low power: <450 mW (under most conditions)

Small package size (5 mm × 5 mm)

Exceeds Telcordia GR-253-CORE jitter generation, transfer

and tolerance specifications

BASIC BLOCK DIAGRAM

REF

PLL

OUTPUT

CIRCUITRY

OUT2

OUT1

PIN DECODER

09057-001

AD9550

Figure 1.

APPLICATIONS

Cost effective replacement of high frequency VCXO, OCXO,

and SAW resonators

Flexible frequency translation for wireline applications such

as Ethernet, T1/E1, SONET/SDH, GPON, xDSL

Wireless infrastructure

Test and measurement (including handheld devices)

GENERAL DESCRIPTION

The AD9550 is a phase-locked loop (PLL) based clock translator

designed to address the needs of wireline communication and

base station applications. The device employs an integer-N PLL

to accommodate the applicable frequency translation requirements.

It accepts a single-ended input reference signal at the REF input.

The AD9550 is pin programmable, providing a matrix of

standard input/output frequency translations from a list of

15 possible input frequencies to a list of 52 possible output

frequency pairs (OUT1 and OUT2).

The AD9550 output is compatible with LVPECL, LVDS, or

single-ended CMOS logic levels, although the AD9550 is

implemented in a strictly CMOS process.

The AD9550 operates over the extended industrial temperature

range of −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

www.analog.com

Tel: 781.329.4700

Fax: 781.461.3113

AD9550

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Basic Block Diagram ........................................................................ 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Output Characteristics ................................................................. 4

Jitter Characteristics ..................................................................... 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Input/Output Termination Recommendations .......................... 11

Theory of Operation ...................................................................... 12

Overview ..................................................................................... 12

Preset Frequencies ...................................................................... 12

Description of Functional Blocks............................................. 15

Jitter Tolerance ............................................................................ 16

Low Dropout (LDO) Regulators .............................................. 16

Automatic Power-On Reset ...................................................... 16

Applications Information .............................................................. 17

Thermal Performance ................................................................ 17

Outline Dimensions ....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

8/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

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