|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PI4MSD5V9542A
2 Channel I2Cbus Multiplexer with interrupt logic
Features
1-of-2 bidirectional translating multiplexer
I2C-bus interface logic
Operating power supply voltage :1.65 V to 5.5 V
Allows voltage level translation between 1.2V,
1.8V,2.5 V, 3.3 V and 5 V buses
Low standby current
Low Ron switches
Channel selection via I2C bus
Power-up with all multiplexer channels deselected
Capacitance isolation when channel disabled
No glitch on power-up
Supports hot insertion
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 8000 V HBM per JESD22-
A114, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard
JESD78 which exceeds 100 mA
Packages offered: SOIC-14W,TSSOP-14L
Description
The PI4MSD5V9542A is a 1-of-2 bidirectional
translating multiplexer, controlled via the I2C bus. The
SCL/SDA upstream pair fans out to two SCx/SDx
downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time,
determined by the contents of the programmable control
register. Two interrupt inputs, INT0 and INT1, one for
each of the SCx/SDx downstream pairs, are provided.
One interrupt output, INT, which acts as an AND of the
two interrupt inputs, is provided.
A power-on reset function puts the registers in their
default state and initializes the I2C bus state machine
with no channels selected.
The pass gates of the multiplexer are constructed
such that the VCC pin can be used to limit the maximum
high voltage which will be passed by the
PI4MSD5V9542A. This allows the use of different bus
voltages on each SCx/SDx pair, so that1.2V, 1.8 V, 2.5
V, or 3.3 V parts can communicate with 5 V parts
without any additional protection. External pull-up
resistors pull the bus up to the desired voltage level for
each channel. All I/O pins are 5 V tolerant.
Pin Configuration
Pin Description
Pin
No
Pin
Name
Type
Input
Input
Input
Input
I/O
I/O
Ground
Input
I/O
I/O
Output
I/O
I/O
Power
Description
1
2
3
4
TSSOP
SOIC
A0
A1
A2
INT0
address input 0
address input 1
address input 2
active LOW interrupt input 0
serial data 0
serial clock 0
supply ground
active LOW interrupt input 1
serial data 1
serial clock 1
active LOW interrupt output
serial clock line
serial data line
supply voltage
5
6
7
8
9
10
11
12
13
14
SD0
SC0
GND
INT1
SD1
SC1
INT
SCL
SDA
VCC
2015-07-0033
1
PT0523-4
8/18/15
PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Block Diagram
Figure 1: Block Diagram
Maximum Ratings
Storage Temperature .................................................–55° to +125°
C
C
Supply Voltage port B .................................................–0.5V to +6.0V
Supply Voltage port A ................................................–0.5V to +6.0V
DC Input Voltage ....................................................... –0.5V to +6.0V
Control Input Voltage (EN)… .................................. –0.5V to +6.0V
Total power dissipation
(1)
.......................................................100mW
Input current(EN,VCCA,VCCB,GND).....................................50mA
ESD: HBM Mode .....................................................................8000V
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sec-
tions of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
Recommended operation conditions
Symbol
V
CC
V
EN
V
IO
Δt /ΔV
T
A
Enable Control Pin Voltage
I/O Pin Voltage
Input transition rise or fall time
Operating Temperature Range
Parameter
V
CCA
Positive DC Supply Voltage
Min
1.65
GND
GND
-
−40
Typ
-
-
-
-
-
Max
5.5
5.5
5.5
10
+85
Unit
V
V
V
ns/V
°
C
2015-07-0033
2
PT0523-4
8/18/15
PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
DC Electrical Characteristics
Unless otherwise specified, -40°C≤T
A
≤85° 1.1V≤Vcc≤3.6V
C,
Symbol
Supply
VCC
Supply Voltage
operating mode;
no load;
V
I
= VCC or GND;
fSCL = 100 kHz
standby mode; VCC =
3.6 V;
no load; V
I
= VCC or
GND;
fSCL = 0 kHz
no load; V
I
= VCC or
GND
3.6V to 5.5V
2.3V to 3.6V
1.65V to 2.3V
3.6V to 5.5V
2.3V to 3.6V
1.65V to 2.3V
3.6V to 5.5V
1.65
65
20
10
0.3
0.1
0.1
1.3
5.5
100
50
30
1
1
1
1.5
V
uA
uA
uA
uA
uA
uA
V
Parameter
Conditions
VCC
Min
Typ
Max
Unit
ICC
supply current
Istb
standby current
VPOR
[1]
power-on reset voltage
Input SCL; input/output SDA
V
IL
V
IH
LOW-level input voltage
HIGH-level input voltage
V
OL
= 0.4 V
V
OL
= 0.6 V
V
I
= GND
V
I
= VCC
VI = GND
1.65V to 5.5V
1.65V to 2V
2V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
-0.5
0.75V
CC
0.7V
CC
3
6
-1
-1
-
9
+0.3V
CC
6
6
-
-
+1
+1
10
V
V
V
mA
mA
uA
uA
pF
Ω
Ω
Ω
Ω
V
4.5
2.2
1.6
1.5
1.1
0.9
0.54
1.3
2
2.8
V
V
V
V
V
V
V
I
OL
I
IL
I
IH
Ci
Pass Gate
LOW-level output current
LOW-level input current
HIGH-level input current
input capacitance
V
O
= 0.4 V;
I
O
= 15 mA
Ron
ON-state resistance
V
O
= 0.4 V;
I
O
= 10mA
4.5 V to 5.5 V
3V to 3.6V
2.3V to 2.7V
1.65V to 2V
5V
4.5 V to 5.5 V
3.3V
4
5
7
9
9
11
16
20
3.6
24
31
55
70
2.8
Vpass
switch output voltage
Vin =VCC;
Iout = -100uA
3V to 3.6V
2.5V
2.3V to 2.7V
1.8V
1.65V to 2V
To be continued
2015-07-0033
3
PT0523-4
8/18/15
PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Continued
Symbol
I
L
Cio
Parameter
leakage current
input/output capacitance
Conditions
VI = VCC or GND
VI = VCC or GND
VCC
1.65V to 5.5V
1.65V to 5.5V
Min
-1
3
Typ
Max
+1
5
Unit
pF
pF
Select inputs A0, A1, A2, INT0, INT1
V
IL
V
IH
I
LI
Ci
INT output
I
OL
I
OH
LOW-level output current
HIGH-level output current
V
OL
= 0.4 V
1.65V to 5.5V
1.65V to 5.5V
3
+10
mA
uA
LOW-level input voltage
HIGH-level input voltage
input leakage current
input capacitance
V
I
= GND
V
I
= GND
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
-0.5
0.7V
CC
-1
3
+0.3V
CC
6
+1
5
V
V
uA
pF
Note:
VCC must be lowered to 0.2 V for at least 5 us in order to reset part.
AC Electrical characteristics
Tamb = - 40
ºC
to +85
ºC;
unless otherwise specified.
Symbol
t
PD[1]
INT
[2]
t
V_INT
t
D_INT
t
REJ_L
valid time from INTn to
INT signal
delay time from INTn to
INT inactive
LOW-level rejection time
1.65V to 5.5V
1.65V to 5.5V
1.65V to 5.5V
1
4
2
us
us
us
us
Parameter
propagation delay
Conditions
from SDA to SDx,
or SCL to SCx
VCC
1.65V to 5.5V
Min
Typ
Max
0.3
Unit
ns
t
REJ_H
HIGH-level rejection time
1.65V to 5.5V
0.5
Note
[1]Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15 pF load capacitance.
[2] Measurements taken with 1 kΩpull-up resistor and 50 pF load.
2015-07-0033
4
PT0523-4
8/18/15
PI4MSD5V9542A
2 Channel I2C bus Multiplexer
with Interrupt Logic
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
I2C Interface Timing Requirements
Symbol
fscl
t
Low
t
High
t
SP
t
SU:DAT
t
HD:DAT
tr
tf
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
VD:DAT
Parameter
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
Valid-data time (high to low)
[2]
SCL low to SDA output low valid
Valid-data time (low to high)
[2]
SCL low to SDA output high valid
Valid-data time of ACK condition
ACK signal from SCL low to SDA output low
I2C bus capacitive load
4.7
4.7
4
4
1
0.6
250
0
[1]
1000
300
1.3
0.6
0.6
0.6
1
0.6
STANDARD MODE
I
2
C BUS
MIN
MAX
FAST MODE
I
2
C BUS
MIN
MAX
UNIT
0
4.7
4
100
0
1.3
0.6
400
kHz
μs
μs
50
100
0
[1]
50
ns
ns
μs
300
300
ns
ns
μs
μs
μs
μs
μs
μs
μs
pF
t
VD:ACK
Cb
1
400
1
400
Notes:
[1] A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL
signal), in order to bridge the undefined region of the falling edge of SCL.
[2] Data taken using a 1-kΩ pullup resistor and 50-pF load Notes
Figure 2. Definition of timing on the I2C-bus
2015-07-0033
5
PT0523-4
8/18/15
Analog electronics
京公网安备 11010802033920号
EEWORLD
