November 09, 2018
W65C816S
8/16–bit Microprocessor
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the best possible product. Information contained herein is provided gratuitously and without liability, to any
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Sales and Sales Policies, copies of which are available upon request.
Copyright (C) 1981-2018 by The Western Design Center, Inc. All rights reserved, including the right of
reproduction in whole or in part in any form.
November 09, 2018
TABLE OF CONTENTS
1
2
INTRODUCTION ...................................................................................................... 5
1.1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
Features of the W65C816S ......................................................................................................... 5
Instruction Register (IR) ............................................................................................................. 6
Timing Control Unit (TCU) .......................................................................................................... 6
Arithmetic and Logic Unit (ALU)................................................................................................ 6
Accumulator (A) .......................................................................................................................... 6
Data Bank Register (DBR) .......................................................................................................... 6
Direct (D) ...................................................................................................................................... 7
Index (X and Y) ............................................................................................................................ 7
Processor Status Register (P) ................................................................................................... 7
Program Bank Register (PBR) ................................................................................................... 7
Program Counter (PC) ................................................................................................................ 7
Stack Pointer (S) ......................................................................................................................... 7
Pin Function Description .......................................................................................................... 10
Abort (ABORTB) ........................................................................................................................ 12
Address Bus (A0-A15) .............................................................................................................. 12
Bus Enable (BE) ........................................................................................................................ 12
Data/Bank Address Bus (D0-D7) ............................................................................................. 13
Emulation Status (E) ................................................................................................................. 13
Interrupt Request (IRQB) .......................................................................................................... 13
Memory Lock (MLB) .................................................................................................................. 13
Memory/Index Select Status (MX) ........................................................................................... 13
Non-Maskable Interrupt (NMIB) ............................................................................................... 14
Phase 2 In (PHI2) ....................................................................................................................... 14
Read/Write (RWB) ..................................................................................................................... 14
Ready (RDY)............................................................................................................................... 14
Reset (RESB) ............................................................................................................................. 15
Valid Data Address (VDA) and Valid Program Address (VPA) ............................................. 15
VDD and VSS ............................................................................................................................. 15
Vector Pull (VPB) ....................................................................................................................... 15
W65C816S FUNCTIONAL DESCRIPTION ............................................................. 6
3
ADDRESSING MODES ......................................................................................... 16
3.1
Reset and Interrupt Vectors ..................................................................................................... 16
3.2
Stack ........................................................................................................................................... 16
3.3
Direct .......................................................................................................................................... 16
3.4
Program Address Space .......................................................................................................... 16
3.5
Data Address Space ................................................................................................................. 16
3.5.1 Absolute-a ................................................................................................................................. 17
3.5.2 Absolute Indexed Indirect-(a,x) ................................................................................................. 17
3.5.3 Absolute Indexed with X-a,x ...................................................................................................... 17
3.5.4 Absolute Indexed with Y-a,y ...................................................................................................... 17
3.5.5 Absolute Indirect-(a) .................................................................................................................. 18
3.5.6 Absolute Long Indexed With X-al,x ........................................................................................... 18
3.5.7 Absolute Long-al........................................................................................................................ 18
3.5.8 Accumulator-A ........................................................................................................................... 18
3.5.9 Block Move-xyc ......................................................................................................................... 19
3.5.10 Direct Indexed Indirect-(d,x) .................................................................................................... 19
3.5.11 Direct Indexed with X-d,x ........................................................................................................ 20
3.5.12 Direct Indexed with Y-d,y ........................................................................................................ 20
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November 09, 2018
3.5.13 Direct Indirect Indexed-(d),y .................................................................................................... 20
3.5.14 Direct Indirect Long Indexed-[d],y ........................................................................................... 21
3.5.15 Direct Indirect Long-[d] ............................................................................................................ 21
3.5.16 Direct Indirect-(d) ..................................................................................................................... 21
3.5.17 Direct-d .................................................................................................................................... 22
3.5.18 Immediate-# ............................................................................................................................. 22
3.5.19 Implied-i ................................................................................................................................... 22
3.5.20 Program Counter Relative Long-rl ........................................................................................... 22
3.5.21 Program Counter Relative-r .................................................................................................... 22
3.5.22 Stack-s ..................................................................................................................................... 22
3.5.23 Stack Relative-d,s.................................................................................................................... 23
3.5.24 Stack Relative Indirect Indexed-(d,s),y.................................................................................... 23
4
TIMING, AC AND DC CHARACTERISTICS ......................................................... 25
4.1
4.2
Absolute Maximum Ratings ..................................................................................................... 25
DC Characteristics TA = -40°C to +85°C ................................................................................ 25
5
6
OPERATION TABLES........................................................................................... 29
RECOMMENDED W65C816S ASSEMBLER SYNTAX STANDARDS ................. 45
6.1
Directives ................................................................................................................................... 45
6.2
Comments .................................................................................................................................. 45
6.3
The Source Line ........................................................................................................................ 45
6.3.1
The Label Field.................................................................................................................... 45
6.3.2
The Operation Code Field ................................................................................................... 45
6.3.3
The Operand Field .............................................................................................................. 46
6.3.4
Comment Field .................................................................................................................... 48
7
Caveats ................................................................................................................. 49
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
7.21
7.22
7.23
Stack Addressing ...................................................................................................................... 50
Direct Addressing ..................................................................................................................... 50
Absolute Indexed Addressing ................................................................................................. 50
ABORTB Input ........................................................................................................................... 50
VDA and VPA Valid Memory Address Output Signals .......................................................... 50
DB/BA operation when RDY is Pulled Low ............................................................................ 51
MX Output .................................................................................................................................. 51
All Opcodes Function in All Modes of Operation .................................................................. 51
Indirect Jumps ........................................................................................................................... 51
Switching Modes ....................................................................................................................... 51
How Interrupts Affect the Program Bank and the Data Bank Registers ............................. 51
Binary Mode ............................................................................................................................... 52
Wait for Interrupt (WAI) Instruction .......................................................................................... 52
Stop-the-Clock (STP) Instruction ............................................................................................. 52
Co-Processor (COP) Signatures .............................................................................................. 52
WDM Opcode Use ..................................................................................................................... 52
RDY Pulled During Write .......................................................................................................... 52
MVN and MVP Affects on the Data Bank Register ................................................................. 52
Interrupt Priorities ..................................................................................................................... 53
Transfers from 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers ................................................... 53
Stack Transfers ......................................................................................................................... 53
BRK Instruction ......................................................................................................................... 53
Accumulator switching from 8-bit to 16-bit ............................................................................ 53
W65C816 Core Information ...................................................................................................... 54
8
9
HARD CORE MODEL ........................................................................................... 54
8.1
SOFT CORE RTL MODEL .................................................................................... 54
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November 09, 2018
9.1
W65C816 Synthesizable RTL-Code in Verilog HDL ............................................................... 54
10
ORDERING INFORMATION ............................................................................... 55
Table of Tables
Table 2-1 W65C816S Microprocessor Programming Model ............................................................................................... 9
Table 2-2 Pin Function Table
......................................................................................................................................... 12
Table 3-1 Addressing Mode Summary
.......................................................................................................................... 24
Table 4-1 Absolute Maximum Ratings
.......................................................................................................................... 25
Table 4-2 W65C816S AC Characteristics
...................................................................................................................... 27
Table 5-1 W65C816S Instruction Set-Alphabetical Sequence ......................................................................................... 29
Table 5-2 Emulation Mode Vector Locations (8-bit Mode) ............................................................................................... 30
Table 5-3 Native Mode Vector Locations (16-bit Mode) ................................................................................................... 30
Table 5-4 Opcode Matrix................................................................................................................................................... 31
Table 5-5 Operation, Operation Codes, and Status Register ............................................................................................ 32
Table 6-1 Alternate Mnemonics ......................................................................................................................................... 46
Table 6-2 Address Mode Formats .................................................................................................................................... 47
Table 6-3 Byte Selection Operator
................................................................................................................................ 48
Table 7-1 Caveats
............................................................................................................................................................ 49
Table of Figures
Figure 2-1 W65C816S Internal Architecture Simplified Block Diagram .............................................................................. 8
Figure 2-2 W65C816S 40 Pin DIP Pinout ......................................................................................................................... 10
Figure 2-3 W65C816S 44 Pin PLCC Pinout ..................................................................................................................... 10
Figure 2-4 W65C816S 44 PIN QFP Pinout ....................................................................................................................... 11
Figure 4-1 General Timing Diagram ................................................................................................................................. 28
Figure 5-1 Bank Address Latching Circuit
...................................................................................................................... 44
4
November 09, 2018
1 INTRODUCTION
The W65C816S is a low power cost sensitive 8/16-bit microprocessor. The variable length instruction set
and manually optimized core size makes the W65C816S an excellent choice for low power System-on-Chip
(SoC) designs. The Verilog RTL model is available for ASIC design flows. WDC, a Fabless Semiconductor
Company, provides packaged chips for evaluation or volume production. To aid in system development,
WDC provides a Professional Software Development Kit (ProSDK) that is available for free download on a
trial basis, see www.westerndesigncenter.com for more information.
The WDC W65C816S is a fully static CMOS 16-bit microprocessor featuring software compatibility* with the
8-bit NMOS and CMOS 6500-series predecessors. The W65C816S extends addressing to a full 16
megabytes. These devices offer the many advantages of CMOS technology, including increased noise
immunity, higher reliability, and greatly reduced power requirements. A software switch determines whether
the processor is in the 8-bit "emulation" mode, or in the native mode, thus allowing existing systems to use
the expanded features.
As shown in the W65C816S Processor Programming Model, Table 2-1, the Accumulator, ALU, X and Y
Index registers, and Stack Pointer register have all been extended to 16 bits. A new 16-bit Direct Page
register augments the Direct Page addressing mode (formerly Zero Page addressing). Separate Program
Bank and Data Bank registers provide 24-bit memory addressing with segmented or linear addressing.
Four new signals provide the system designer with many options. The ABORTB input can interrupt the
currently executing instruction without modifying internal register, thus allowing virtual memory system
design. Valid Data Address (VDA) and Valid Program Address (VPA) outputs facilitate dual cache memory
by indicating whether a data segment or program segment is accessed. Modifying a vector is made easy by
monitoring the Vector Pull (VPB) output.
1.1
Features of the W65C816S
Advanced fully static CMOS design for low power
Low power consumption (300uA@1MHz)
consumption and increased noise immunity
Separate program and data bank registers allow
Wide operating voltage range, 1.8+/- 5%, 2.5+/-
program segmentation or full 16 MByte linear
5%, 3.0+/- 5%, 3.3+/- 10%, 5.0+/- 5% specified for
addressing
use with advanced low voltage peripherals
New Direct Register and stack relative addressing
Emulation mode allows complete hardware and
provides capability for re-entrant, re-cursive and re-
software compatibility with 65xx designs
locatable programming
24-bit address bus provides access to 16 MBytes
24 addressing modes - 13 original W65C02S
of memory space
modes with 92 instructions using 256 opcodes
Full 16-bit ALU, Accumulator, Stack Pointer and
Wait for Interrupt (WAI) and Stop-the-Clock (STP)
Index Registers
instructions further reduce power consumption,
decrease interrupt latency and allows synchronization
Valid Data Address (VDA) and Valid Program
with external events
Address (VPA) output for dual cache and cycle steal
DMA implementation
Co-Processor (COP) instruction with associated
vector supports co-processor configurations, i.e.,
Vector Pull (VPB) output indicates when interrupt
floating point processors
vectors are being addressed
Block move ability
Abort (ABORTB) input and associated vector
supports processor repairs of bus error conditions
*
Except for the BBRx, BBSx, RMBx, and SMBx bit manipulation instructions which do not exist for the
W65C816S
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