dsPIC33CH128MP203-I/M5 datasheet, PDF

Datasheet> All Categories > semiconductor> The embedded processor and controller> Digital signal processor and controller - DSP, DSC> dsPIC33CH128MP203-I/M5

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dsPIC33CH128MP203-I/M5: DescriptionDigital Signal Processor and Controller-DSP, DSC 16 Bit DSC, Dual Core, 128K Flash, 16K+ 4K RAM, 100MHz, 36Pin; Categorysemiconductor The embedded processor and controller Digital signal processor and controller - DSP, DSC; File Size5MB，809 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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dsPIC33CH128MP203-I/M5 Overview

Digital Signal Processor and Controller-DSP, DSC 16 Bit DSC, Dual Core, 128K Flash, 16K+ 4K RAM, 100MHz, 36Pin

dsPIC33CH128MP203-I/M5 Parametric

Parameter Name	Attribute value
Maker	Microchip
Product Category	Digital Signal Processors and Controllers - DSP, DSC
Installation style	SMD/SMT
Package/box	UQFN-36
series	dsPIC33CH
product	DSCs
core	dsPIC33CH
maximum clock frequency	180 MHz, 200 MHz
Program memory size	24 kB, 128 kB
Data RAM size	4 kB, 16 kB
Working power voltage	3 V to 3.6 V
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
Encapsulation	Tube
Program memory type	Flash
Interface Type	CAN, I2C, I2S, SPI, UART
Data bus width	16 bit
Instruction type	Fixed/Floating Point
Number of cores	2 Core
Number of timers/counters	1 Timer
Factory packaging quantity	73
Supply voltage - max.	3.6 V
Supply voltage - min.	3 V
watchdog timer	Watchdog Timer

User Manual

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dsPIC33CH128MP508 FAMILY

28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data (CAN FD)

Operating Conditions

• 3V to 3.6V, -40°C to +125°C:

- Master Core: DC to 90 MIPS

- Slave Core: DC to 100 MIPS

Power Management

• Low-Power Management Modes

(Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

Core: Dual 16-Bit dsPIC33CH CPU

• Master/Slave Core Operation

• Independent Peripherals for Master Core and

Slave Core

• Dual Partition for Slave PRAM LiveUpdate

• Configurable Shared Resources for Master Core

and Slave Core

• Master Core with 64-128 Kbytes of Program

Flash with ECC and 16K RAM

• Slave Core with 24 Kbytes of Program RAM

(PRAM) with ECC and 4K Data Memory RAM

• Fast 6-Cycle Divide

• Message Boxes and FIFO to Communicate

Between Master and Slave (MSI)

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus Hardware

Divide

• 32-Bit Multiply Support

• Five Sets of Interrupt Context Selected Registers

and Accumulators per Core for Fast Interrupt

Response

• Zero Overhead Looping

High Resolution PWM with Fine Edge

Placement

• Up to 12 PWM Channels:

- Four channels for Master

- Eight channels for Slave

• 250 ps PWM Resolution

• Applications Include:

- DC/DC Converters

- AC/DC power supplies

- Uninterruptable Power Supply (UPS)

- Motor Control: BLDC, PMSM, SR, ACIM

Timers/Output Compare/Input Capture

• Two General Purpose 16-Bit Timers:

- One each for Master and Slave

• Peripheral Trigger Generator (PTG) Module:

- One module for Master

- Slave can interrupt on select PTG sources

- Useful for automating complex sequences

• 12 SCCP Modules:

- Eight modules for Master

- Four modules for Slave

- Timer, Capture/Compare and PWM Modes

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

- Fully Asynchronous Operation, Available in

Sleep Modes

Clock Management

• Internal Oscillator

• Programmable PLLs and Oscillator Clock

Sources

• Master Reference Clock Output

• Slave Reference Clock Output

• Fail-Safe Clock Monitor (FSCM)

• Fast Wake-up and Start-up

• Backup Internal Oscillator

• LPRC Oscillator



2017-2018 Microchip Technology Inc.

DS70005319B-page 1

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