dsPIC33CH128MP208-E/PT datasheet, PDF

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dsPIC33CH128MP208-E/PT: DescriptionDigital Signal Processor and Controller-DSP, DSC 16 Bit DSC, Dual Core, 128K Flash, 16K+ 4K RAM, 100MHz, 80Pin, E-temp; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，809 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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dsPIC33CH128MP208-E/PT Overview

Digital Signal Processor and Controller-DSP, DSC 16 Bit DSC, Dual Core, 128K Flash, 16K+ 4K RAM, 100MHz, 80Pin, E-temp

dsPIC33CH128MP208-E/PT Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	TQFP-80
Reach Compliance Code	compliant
Factory Lead Time	5 weeks
Other features	4k bytes internal data ram in slave core available
barrel shifter	YES
bit size	16
boundary scan	YES
maximum clock frequency	64 MHz
Format	FLOATING POINT
Integrated cache	NO
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQFP-G80
length	12 mm
low power mode	YES
Number of external interrupt devices	4
Number of terminals	80
On-chip data RAM width	8
On-chip program ROM width	8
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP64,.55SQ
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
RAM (number of words)	8192
ROM programmability	FLASH
Filter level	AEC-Q100; TS 16949
Maximum seat height	1.2 mm
Maximum slew rate	300 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	12 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

User Manual

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dsPIC33CH128MP508 FAMILY

28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data (CAN FD)

Operating Conditions

• 3V to 3.6V, -40°C to +125°C:

- Master Core: DC to 90 MIPS

- Slave Core: DC to 100 MIPS

Power Management

• Low-Power Management Modes

(Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

Core: Dual 16-Bit dsPIC33CH CPU

• Master/Slave Core Operation

• Independent Peripherals for Master Core and

Slave Core

• Dual Partition for Slave PRAM LiveUpdate

• Configurable Shared Resources for Master Core

and Slave Core

• Master Core with 64-128 Kbytes of Program

Flash with ECC and 16K RAM

• Slave Core with 24 Kbytes of Program RAM

(PRAM) with ECC and 4K Data Memory RAM

• Fast 6-Cycle Divide

• Message Boxes and FIFO to Communicate

Between Master and Slave (MSI)

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus Hardware

Divide

• 32-Bit Multiply Support

• Five Sets of Interrupt Context Selected Registers

and Accumulators per Core for Fast Interrupt

Response

• Zero Overhead Looping

High Resolution PWM with Fine Edge

Placement

• Up to 12 PWM Channels:

- Four channels for Master

- Eight channels for Slave

• 250 ps PWM Resolution

• Applications Include:

- DC/DC Converters

- AC/DC power supplies

- Uninterruptable Power Supply (UPS)

- Motor Control: BLDC, PMSM, SR, ACIM

Timers/Output Compare/Input Capture

• Two General Purpose 16-Bit Timers:

- One each for Master and Slave

• Peripheral Trigger Generator (PTG) Module:

- One module for Master

- Slave can interrupt on select PTG sources

- Useful for automating complex sequences

• 12 SCCP Modules:

- Eight modules for Master

- Four modules for Slave

- Timer, Capture/Compare and PWM Modes

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

- Fully Asynchronous Operation, Available in

Sleep Modes

Clock Management

• Internal Oscillator

• Programmable PLLs and Oscillator Clock

Sources

• Master Reference Clock Output

• Slave Reference Clock Output

• Fail-Safe Clock Monitor (FSCM)

• Fast Wake-up and Start-up

• Backup Internal Oscillator

• LPRC Oscillator



2017-2018 Microchip Technology Inc.

DS70005319B-page 1

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