dsPIC33CH128MP206-I/PT datasheet, PDF

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dsPIC33CH128MP206-I/PT: DescriptiondsPIC33 100MHz Dual Core 64-Pin 128KB Flash; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，809 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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dsPIC33CH128MP206-I/PT Overview

dsPIC33 100MHz Dual Core 64-Pin 128KB Flash

dsPIC33CH128MP206-I/PT Parametric

Parameter Name	Attribute value
Objectid	145117219623
package instruction	TQFP-64
Reach Compliance Code	compliant
Country Of Origin	Thailand
ECCN code	3A991.A.2
Factory Lead Time	52 weeks
Samacsys Description	16 Bit DSC, Dual Core, 128K Flash, 16K+ 4K RAM, 100MHz, 64Pin
Samacsys Manufacturer	Microchip
Samacsys Modified On	2023-03-07 16:10:32
YTEOL	6.5
Other features	4K BYTES INTERNAL DATA RAM IN SLAVE CORE AVAILABLE
Address bus width
barrel shifter	YES
bit size	16
boundary scan	YES
maximum clock frequency	64 MHz
External data bus width
Format	FIXED POINT
Integrated cache	NO
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQFP-G64
length	10 mm
low power mode	YES
Number of DMA channels	8
Number of external interrupt devices	4
Number of serial I/Os	2
Number of terminals	64
Number of timers	5
On-chip data RAM width	8
On-chip program ROM width	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Encapsulate equivalent code	TQFP64,.47SQ
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
RAM (number of words)	16384
ROM programmability	FLASH
Maximum seat height	1.2 mm
Maximum slew rate	63.6 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, CONTROLLER

User Manual

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dsPIC33CH128MP508 FAMILY

28/36/48/64/80-Pin Dual Core, 16-Bit Digital Signal Controllers

with High-Resolution PWM and CAN Flexible Data (CAN FD)

Operating Conditions

• 3V to 3.6V, -40°C to +125°C:

- Master Core: DC to 90 MIPS

- Slave Core: DC to 100 MIPS

Power Management

• Low-Power Management Modes

(Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

Core: Dual 16-Bit dsPIC33CH CPU

• Master/Slave Core Operation

• Independent Peripherals for Master Core and

Slave Core

• Dual Partition for Slave PRAM LiveUpdate

• Configurable Shared Resources for Master Core

and Slave Core

• Master Core with 64-128 Kbytes of Program

Flash with ECC and 16K RAM

• Slave Core with 24 Kbytes of Program RAM

(PRAM) with ECC and 4K Data Memory RAM

• Fast 6-Cycle Divide

• Message Boxes and FIFO to Communicate

Between Master and Slave (MSI)

• Code Efficient (C and Assembly) Architecture

• 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle, Mixed-Sign MUL Plus Hardware

Divide

• 32-Bit Multiply Support

• Five Sets of Interrupt Context Selected Registers

and Accumulators per Core for Fast Interrupt

Response

• Zero Overhead Looping

High Resolution PWM with Fine Edge

Placement

• Up to 12 PWM Channels:

- Four channels for Master

- Eight channels for Slave

• 250 ps PWM Resolution

• Applications Include:

- DC/DC Converters

- AC/DC power supplies

- Uninterruptable Power Supply (UPS)

- Motor Control: BLDC, PMSM, SR, ACIM

Timers/Output Compare/Input Capture

• Two General Purpose 16-Bit Timers:

- One each for Master and Slave

• Peripheral Trigger Generator (PTG) Module:

- One module for Master

- Slave can interrupt on select PTG sources

- Useful for automating complex sequences

• 12 SCCP Modules:

- Eight modules for Master

- Four modules for Slave

- Timer, Capture/Compare and PWM Modes

- 16 or 32-bit time base

- 16 or 32-bit capture

- 4-deep capture buffer

- Fully Asynchronous Operation, Available in

Sleep Modes

Clock Management

• Internal Oscillator

• Programmable PLLs and Oscillator Clock

Sources

• Master Reference Clock Output

• Slave Reference Clock Output

• Fail-Safe Clock Monitor (FSCM)

• Fast Wake-up and Start-up

• Backup Internal Oscillator

• LPRC Oscillator



2017-2018 Microchip Technology Inc.

DS70005319B-page 1

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