Bel Power Solutions point-of-load converters are recommended for
use with regulated bus converters in an Intermediate Bus Architecture
(IBA). The DM73XX is a fully programmable digital power manager that
utilizes the industry-standard I²C communication bus interface to
control, manage, program and monitor up to 32 dP-series POL
converters and 4 independent power devices. The DM73XX
completely eliminates the need for external components for power
management and programming and monitoring of the d-pwer
TM
POL
converters and other industry standard power and peripheral devices.
Parameters of the DM73XX are programmable via the I²C bus and can
be changed by a user at any time during product development and
deployment.
RoHS compliant for all six substances
Compatible with both lead-free and standard reflow processes
Programs, controls, and manages up to 32 independent dPOL
converters via an industry standard I²C interface (both 100 kHz and 400
kHz)
JTAG IEEE 1149.1 compliant programming interface
Controls and monitors industry standard power supplies and other
peripheral devices (fans, etc)
Programs output voltage, protections, optimal voltage positioning, turn-
on and turn-off delays and slew rates, switching frequency, interleave
(phase shift), and feedback loop compensation of the d-pwer
TM
POL
converters
User friendly GUI interface for programming, monitoring, and
performance simulation
Four independent OK lines for flexible fault management and fast fault
propagation
Four interrupt inputs with programmable hot swap support capabilities
Intermediate bus voltage monitoring and protection
AC Fail input
Non-volatile system configuration data memory
1K Byte of user accessible non-volatile memory
Control of industry standard DC-DC front ends
Crowbar output to trigger the optional crowbar protection
Run-time counter
Small footprint semiconductor industry standard QFN64 package:
9x9 mm
Wide industrial operating temperature range
Asia-Pacific
+86 755 298 85888
Europe, Middle East
+353 61 225 977
North America
+1 866 513 2839
© 2015 Bel Power Solutions, Inc.
BCD.00317_AC
2
DPM TYPE
DM7304G
DM7308G
DM7316G
DM7332G
NUMBER OF D-PWER
TM
POLS
AND AUXILIARY DEVICES
THAT CAN BE CONTROLLED
4
8
16
32
ACTIVE
ADDRESSES
00…03
00…07
00…15
00…31
NUMBER OF
GROUPS
2
2
3
4
NUMBER OF
INTERRUPTS
2
2
3
4
NUMBER OF
PARALLEL
BUSES
2
4
4
8
NUMBER OF
AUXILIARY
DEVICES
4
4
4
4
DPM TYPE
DM7304G
DM7308G
DM7316G
DM7332G
DPM PRELOADED WITH DEFAULT
CONFIGURATION FILE
65511
65512
65513
65514
DPM CONFIGURED FOR JTAG
PROGRAMMING
65515
65516
65517
65518
PACKAGING
OPTIONS
B1, R100
B1, R100
B1, R100
B1, R100
Stresses beyond those listed may cause permanent damage to the DPM. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Functional operation of the DPM at absolute maximum ratings or conditions beyond
those indicated in the operational sections of this specification is not implied.
PARAMETER
Ambient Temperature Range
Storage Temperature (Ts)
Junction Temperature (T
J
)
Input Voltage
Input Voltage
Pin Current
VDD pin
Any pin other than VDD
DC
-0.3
-0.5
CONDITIONS / DESCRIPTION
MIN
-40
-55
MAX
85
150
125
3.6
VDD+0.5
40
UNITS
C
C
C
VDC
VDC
mA
PARAMETER
Peak Reflow Temperature
Lead Plating
Moisture Sensitivity Level
CONDITIONS/DESCRIPTION
40 sec maximum duration
MIN
NOM
MAX
260
UNITS
C
100% matte tin
JEDEC J-STD-020C
3
PARAMETER
Failure Rate
Non-Volatile Memory Endurance
CONDITIONS/DESCRIPTION
Demonstrated at 55C, 60% Confidence Level
-40°C to 85°C ambient
MIN
2.26
10000
NOM
MAX
UNITS
FIT
Read-
Write
cycles
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3
Specifications apply at VDD from 3 V to 3.6 V, ambient temperature from -40°C to 85°C, and utilizing proper decoupling as shown
in Figure 3 unless otherwise noted.
6.1 POWER SPECIFICATIONS
Input Supply Voltage
Undervoltage Lockout
Input Supply Current
VREF voltage
IBVS input voltage range
IBVS input resistance
VDD pin
Hardware reset is triggered below this
threshold
VDD pin = 3.3 V
AREF pin
3.0
2.3
2.5
12
2.3
GND
100
2.56
3.6
2.7
20
2.7
VREF
VDC
VDC
mA
VDC
VDC
MΩ
6.2 FEATURE SPECIFICATIONS
PARAMETER
Intermediate Voltage Bus Protections
Overvoltage Protection Threshold
Undervoltage Protection Threshold
Threshold Hysteresis
Accuracy of Protection Thresholds
Internal ADC Conversion Error
With external 5.7:1 ratio divider
With external 5.7:1 ratio divider
With external 5.7; 1ratio divider.
Symmetrical relative to average threshold value
Internal voltage reference, 1% resistive divider
With external 5.7:1 ratio divider
-10
-43
IBV
0
±114
10
43
14.6
IBV
V
V
mV
%V
TH
mV
CONDITIONS/DESCRIPTION
MIN
NOM
MAX
UNITS
Front End Enable (FE_EN)
V
FE_EN
V
FE_EN
Isrc
Isink
Front End logic level enabled
Front End logic level disabled
Source Current, V
FE_EN
= V
DD
-0.5 V
Sink Current, V
FE_EN
= 0.5V
5
5
High
Low
mA
mA
Crowbar (CB)
V
CB
V
CB
Isrc
Isink
T
CB
Crowbar Enable
Crowbar Disable
Source Current, V
CB
= V
DD
-0.5 V
Sink Current, V
CB
= 0.5 V
Duration of Enabling Pulse
5
5
1
High
Low
mA
mA
ms
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6.3 SIGNAL SPECIFICATIONS
PARAMETER
SYNC/DATA Line
SDpu
SDthrL
SDthrH
SDhys
SDsink
Freq_sd
Tsynq
T0
SD pull up resistor
SD input low voltage threshold
SD input high voltage threshold
SD input hysteresis
SD sink capability (V
SD
= 0.5 V)
Clock frequency
Sync pulse duration
Data = 0 pulse duration
450
22
72
0.31·VDD
0.45·VDD
0.37
5
0.52·VDD
0.81·VDD
1.1
30
550
28
78
kΩ
V
V
V
mA
kHz
% of clock
cycle
% of clock
cycle
CONDITIONS / DESCRIPTION
MIN
NOM
MAX
UNITS
Interrupt Inputs (INT_N[3:0])
Rpu3
VthrL3
VthrH3
Vhys3
Pull up resistor
Input low voltage threshold
Input high voltage threshold
Input hysteresis
0.31·VDD
0.45·VDD
0.37
30
0.52·VDD
0.81·VDD
1.1
kΩ
V
V
V
ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs
Rpu1
VthrL1
VthrH1
Pull up resistor
Input low voltage
Input high voltage
20
-0.5
0.7·VDD
50
0.2·VDD
VDD+0.5
kΩ
V
V
HRES_N Input
Rpu2
VthrL2
VthrH2
HRES_N pull up resistor (with series
diode, see note
1
)
HRES_N input low voltage
HRES_N input high voltage
30
-0.5
0.9·VDD
60
0.2·VDD
VDD+0.5
kΩ
V
V
Inputs/Outputs (OK_A, OK_B, OK_C, OK_D)
OKpu
OKthrL
OKthrH
OKhys
OKsink
OK pull up resistor
OK input low voltage threshold
OK input high voltage threshold
OK input hysteresis
OK sink capability (V
OK
= 0.5 V)
0.31·VDD
0.45·VDD
0.37
5
0.52·VDD
0.81·VDD
1.1
30
kΩ
V
V
V
mA
Enable Outputs (EN[3:0])
V
EN
V
EN
V
EN
H
V
EN
L
EN logic level enabled
EN logic level disabled
EN output high voltage (I
OH
= -10 mA)
EN output low voltage (I
OL
= 5 mA)
VDD-0.6
0.5
High
Low
V
V
1
HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode
between the HRES_N and VDD pins as shown in Figure .
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5
6.4 I²C INTERFACE
PARAMETER
ViL
ViH
Vhys
VoL
t
r
t
of
Ii
Ci
f
SCL
CONDITIONS/DESCRIPTION
Input low voltage
Input high voltage
Input hysteresis
Output low voltage, I
SINK
=3mA
Rise time for SDA and SCL
Output fall time from ViHmin to ViLmax
Input current each I/O pin, 0.1V
DD
< V
i
< 0.9 V
DD
Capacitance for each I/O pin
SCL clock frequency
MIN
-0.5
0.7·VDD
0.05·VDD
0
20+0.1C
b2
20+0.1C
b2
-10
NOM
MAX
0.3·VDD
VDD+0.5
UNITS
V
V
V
0.4
300
250
10
10
V
ns
ns
μA
pF
kHz
0
400
Standard-Mode I²C (f
SCL
≤
100kHz)
R
PU
t
HDSTA
t
LOW
t
HIGH
t
SUSTA
t
HDDAT
t
SUDAT
t
SUSTD
t
SUF
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
1
4.0
4.7
4.0
4.7
0
250
4.0
4.7
3.45
1000/C
b2
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
Fast-Mode I²C (100kHz < f
SCL
≤
400kHz)
R
PU
t
HDSTA
t
LOW
t
HIGH
t
SUSTA
t
HDDAT
t
SUDAT
t
SUSTD
t
SUF
External pull-up resistor
Hold time (repeated) START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
1
0.6
1.3
0.6
0.6
0
100
0.6
1.3
0.9
300/C
b2
kΩ
μs
μs
μs
μs
μs
ns
μs
μs
2
C
b
– bus capacitance in pF, typically from 10 pF to 400 pF
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