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dsPIC33CK64MP202-E/SS

Description
Microcontroller
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size4MB,621 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
Download Datasheet Download user manual Parametric View All

dsPIC33CK64MP202-E/SS Overview

Microcontroller

dsPIC33CK64MP202-E/SS Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid8358206950
package instructionSSOP, SSOP28,.3
Reach Compliance Codecompliant
Country Of OriginThailand
ECCN code3A991.A.2
Factory Lead Time6 weeks
Samacsys ManufacturerMicrochip
Samacsys Modified On2022-03-29 01:05:04
YTEOL20.03
Address bus width
barrel shifterYES
bit size16
boundary scanYES
maximum clock frequency64 MHz
External data bus width
FormatFIXED POINT
Integrated cacheNO
Internal bus architectureMULTIPLE
JESD-30 codeR-PDSO-G28
length10.2 mm
low power modeYES
Number of DMA channels4
Number of external interrupt devices4
Number of serial I/Os4
Number of terminals28
Number of timers2
On-chip data RAM width8
On-chip program ROM width24
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP28,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
RAM (number of words)8192
ROM programmabilityFLASH
Filter levelAEC-Q100
Maximum seat height2 mm
Maximum slew rate42.5 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width5.3 mm
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, CONTROLLER
dsPIC33CK256MP508 FAMILY
28/36/48/64/80-Pin, 16-Bit Digital Signal Controllers
with High-Resolution PWM and CAN Flexible Data (CAN FD)
Operating Conditions
• 3.0V to 3.6V, -40°C to +85°C, DC to 100 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 100 MIPS
Power Management
• Low-Power Management Modes (Sleep,
Idle, Doze)
• Integrated Power-on Reset and Brown-out Reset
Core: 16-Bit dsPIC33CK CPU
• 32-256 Kbytes of Program Flash with ECC and
8-24K RAM
• Fast 6-Cycle Divide
• LiveUpdate
• Code Efficient (C and Assembly) Architecture
• 40-Bit Wide Accumulators
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle, Mixed-Sign MUL Plus
Hardware Divide
• 32-Bit Multiply Support
• Four Sets of Interrupt Context Saving Registers
which Include Accumulator and STATUS for Fast
Interrupt Handling
• Zero Overhead Looping
• RAM Memory Built-In Self-Test (MBIST)
High-Speed PWM
8 PWM Pairs
Up to 250 ps PWM Resolution
Dead Time for Rising and Falling Edges
Dead-Time Compensation
Clock Chopping for High-Frequency Operation
PWM Support for:
- DC/DC, AC/DC, inverters, PFC, lighting
- BLDC, PMSM, ACIM, SRM motors
• Fault and Current Limit Inputs
• Flexible Trigger Configuration for ADC Triggering
Timers/Output Compare/Input Capture
• One General Purpose Timer
• Peripheral Trigger Generator (PTG):
- Up to 15 trigger sources to other
peripheral modules
- CPU independent state machine-based
instruction sequencer
• Nine MCCP/SCCP modules which Include Timer,
Capture/Compare and PWM:
- 1 MCCP
- 8 SCCPs
- 16 or 32-bit time base
- 16 or 32-bit capture
- 4-deep capture buffer
• Fully Asynchronous Operation, Available in
Sleep Modes
Clock Management
Internal Oscillator
Programmable PLLs and Oscillator Clock Sources
Reference Clock Output
Fail-Safe Clock Monitor (FSCM)
Fast Wake-up and Start-up
Backup Internal Oscillator
2017-2018 Microchip Technology Inc.
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