FemtoClock
®
NG Clock Generator
with Four Dividers
8V49NS0412
Datasheet
Description
The 8V49NS0412 is a clock generator with four output dividers:
three integers, and one that is either integer or fractional. When
used with an external crystal, the 8V49NS0412 generates
high-performance timing for the communications and datacom
markets, especially for applications that demand extremely low
phase noise, such as 10GE, 40GE, 100G, and 400GE.
The 8V49NS0412 provides versatile frequency configurations and
output formats, and is optimized to deliver excellent phase noise
performance. The device delivers an optimum combination of high
clock frequency and low phase noise performance, combined with
high power supply noise rejection.
The 8V49NS0412 supports two types of output levels: LVPECL or
LVDS on eleven of its outputs. In addition, the device has a single
LVCMOS output that can provide a generated clock, or act as a
reference bypass output.
The device can be configured to deliver specific configurations
under pin control only, or additional configurations through an I
2
C
serial interface by external processor, or an external I
2
C EEPROM
to loading the configuration.
Features
▪
Eleven differential LVPECL and LVDS outputs with
programmable voltage swings
▪
One LVCMOS output: Input reference can be passed to this
output
▪
The clock input operates in full differential mode (LVDS,
LVPECL) or single-ended LVCMOS mode
▪
Driven from a crystal or differential clock input
▪
2.4–2.5GHz PLL frequency range supports Ethernet, SONET,
and CPRI frequency plans
▪
Four Integer output dividers with a range of output divide ratios
(see
Table 5)
▪
One Fractional output divider can generate any desired output
frequency
▪
Support of output power-down
▪
Excellent clock output phase noise:
Offset Output Frequency Single-side Band Phase Noise
100kHz
156.25MHz
-143dBc/Hz
▪
RMS phase noise, 12kHz to 20MHz integration range:
110fs (maximum) at 156.25MHz
▪
Selected configurations can be controlled via the control input
pins without need for serial port access
▪
LVCMOS compatible I
2
C serial interface gives access to
additional configuration by external processor or loading the
configuration from an external I
2
C EEPROM, or in combination
with the control input pins
▪
Single 3.3V supply voltage
▪
64-VFQFN 9
9 mm, lead-free (RoHS 6) package
▪
-40°C to 85°C ambient operating temperature
Typical Applications
▪
▪
▪
▪
10G/40G/100/400G Ethernet
Fiber optics
Gigabit Ethernet, Terabit IP switches/routers
CPRI Interfaces
©2018 Integrated Device Technology, Inc.
1
March 21, 2018
8V49NS0412 Datasheet
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin versus Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Input Clock Selection (REF_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Prescaler and PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PLL Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Divider Frequency Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Integer Output Dividers (Banks A, B, C, and D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Fractional Output Divider (Bank D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Control of the Output Frequencies and Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Start-up and Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Control Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Control Port Configuration Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2C Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I
2
C Master Mode Operation and Device Start-up Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Overdriving the XTAL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wiring the Differential Input to Accept Single-Ended Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.3V Differential Clock Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
VFQFN EPAD Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Schematic and Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power Dissipation and Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Example 1. LVPECL, 750mV Output Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Example 2. LVDS, 350mV Output Swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reliability Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
©2018 Integrated Device Technology, Inc.
2
March 21, 2018
8V49NS0412 Datasheet
Block Diagram
Figure 1: 8V49NS0412 Block Diagram
REF_SEL
Pulldown
CLK
PU/PD
nCLK
XTAL_IN
OSC
XTAL_OUT
Pulldown
LOCK
QA0
nQA0
2400
– 2500MHz
IntN PLL
QA1
IntN Div A
nQA1
QA2
nQA2
QA3
nQA3
FDP
and
PS
FIN[1:0]
PU/PD
NA[1:0]
PU/PD
NB[1:0]
PU/PD
NC[1:0]
PU/PD
ND[1:0]
PU/PD
Status and
Control Registers
IntN Div B
QB0
nQB0
QB1
nQB1
QB2
nQB2
Power-up
Reset
QB3
nQB3
QC0
nQC0
IntN Div C
IntN Div D
FracN Div D
FDIV
QC1
nQC1
QD0
nQD0
QD1
SCLK
SDATA
Pullup
Pullup
I
2
C Master
and Slave
Transistor count: 132,756
©2018 Integrated Device Technology, Inc.
3
March 21, 2018
8V49NS0412 Datasheet
Pin Assignments
Figure 2: Pin Assignments for 9
9 mm 64-Lead VFQFN Package
—
Top View
REF_SEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
CAP
XTAL
SDATA
V
CCA_XT
OSCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
CCOB
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
V
CCOB
ND[0]
ND[1]
V
CCOD
QD1
QD0
nQD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
V
CC_CK
V
CC_SP
LOCK
FIN[0]
FIN[1]
SCLK
nCLK
NA[0]
OSCI
RES
CLK
V
CCOA
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
V
CCOA
V
CCOC
QC0
nQC0
QC1
nQC1
V
CCOC
8V49NS0412
CAP
BIAS
CAP
REG
V
CCA_IN1
V
CCA_IN2
Pin Descriptions
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
Name
V
CCOB
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
V
CCOB
ND[0]
Type
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input [PU/PD]
Description
Power supply voltage for output Bank B (3.3V).
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Power supply voltage for output Bank B (3.3V).
Control input for output Bank D. 3-level signals (see
Table 10).
©2018 Integrated Device Technology, Inc.
4
V
CC_CP
ICP
NB[0]
NB[1]
NC[0]
NC[1]
NA[1]
CR
LFF
LFFR
V
CCA
nc
March 21, 2018
8V49NS0412 Datasheet
Table 1. Pin Descriptions (Cont.)
Number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Name
ND[1]
V
CCOD
QD1
QD0
nQD0
NB[0]
NB[1]
NC[0]
NC[1]
V
CCA_IN1
NA[1]
CAP
BIAS
V
CCA_IN2
CR
CAP
REG
LFFR
LFF
V
CCA
nc
V
CC_CP
ICP
V
CCOC
nQC1
QC1
nQC0
QC0
V
CCOC
V
CCOA
nQA3
QA3
nQA2
QA2
Type
Input [PU/PD]
Power
Output
Output
Output
Input [PU/PD]
Input [PU/PD]
Input [PU/PD]
Input [PU/PD]
Power
Input [PU/PD]
Analog
Power
Analog
Analog
Analog
Output
Power
-
Power
Analog
Power
Output
Output
Output
Output
Power
Power
Output
Output
Output
Output
Description
Control input for output Bank D. 3-level signals (see
Table 10).
Power supply voltage for output Bank D (3.3V).
Single-ended output clock. LVCMOS output levels.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Control input for output Bank B. 3-level signals (see
Table 8).
Control input for output Bank B. 3-level signals (see
Table 8).
Control input for output Bank C. 3-level signals (see
Table 9).
Control input for output Bank C. 3-level signals (see
Table 9).
Analog power supply voltage for PLL (3.3V).
Control input for output Bank A. 3-level signals (see
Table 7).
Internal VCO bias decoupling capacitor. Use a 4.7µF capacitor between the CAP
BIAS
terminal and V
EE.
Analog power supply voltage for VCO (3.3V).
Internal VCO regulator decoupling capacitor. Use a 1µF capacitor between the CR and
the V
CCA
terminals.
Internal VCO regulator decoupling capacitor. Use a 4.7µF capacitor between the CAP
REG
terminal and V
EE.
Ground return path pin for the PLL loop filter.
Loop filter/charge pump output for the FemtoClock NG PLL. Connect to the external loop
filter.
Analog power supply voltage for VCO (3.3V).
No connect. Do not use.
Analog power supply voltage for PLL charge pump (3.3V).
Charge pump current input for PLL. Connect to LFF pin (28).
Power supply voltage for output Bank C (3.3V).
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Power supply voltage for output Bank C (3.3V).
Power supply voltage for output Bank A (3.3V).
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
Differential clock output pair. LVPECL or LVDS with configurable amplitude.
©2018 Integrated Device Technology, Inc.
5
March 21, 2018
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