Critical Link, LLC
www.CriticalLink.com
MitySOM
MitySOM-5CSx System on Module
19 November 2014
FEATURES
Altera Cyclone V - U672 SoC
-
Up To Dual ARM Cortex- A9 MPU
-
925MHz Max clock speed
-
Dual NEON SIMD Coprocessors
-
32 KB L1 Program Cache (per core)
-
32 KB L1 Data Cache (per core)
-
512 KB L2 Cache (shared)
-
64 KB on-chip RAM
-
ECC Support
-
Up To 133 User FPGA I/O Pins
-
44 CPU I/O Pins
-
6 High speed transceivers (SX only)
Cyclone V Processor Choices
-
Cyclone V SX (3.125 Gbps transceivers)
-
Cyclone V SE
Memory
-
Up To 2GB DDR3 CPU RAM
x32 bits + ECC
-
Up To 512MB DDR3 FPGA RAM
x8 bits (optional)
-
Up To 48MB QPSI NOR FLASH
Integrated Power Management
JTAG connector on-module
FPGA Fabric
-
Up To 110K Logic Elements (LE)
-
460Mhz Global Clock
-
Up To 5.1Mb M10K Memory
-
Up To 621Kb MLAB Memory
-
Up To 112 DSP Blocks
-
Up To 6 FPGA PLLs
-
Fractional PLL Outputs on each PLL
Low Power Serial Transceivers (SX
only)
-
3.125Gbps Transceivers
-
PCIe Hard IP Block
(Gen1.1 x1 or x4)
Power, Reset and Clock Management
Mechanical
-
314-Pin Card Edge Connector
-
Small 82mm (3.2”) x 39mm (1.5”) size
Hard Processor System (HPS)
-
Selection of boot sources
-
Up to 2 10/100/1000 Mbps RGMII
-
Up to 2 USB 2.0 OTG Ports
-
Up to 2 CAN Interfaces
-
Up to 2 UARTs
-
1 MMC/SD/SDIO
-
Up to 4 I2C controllers
-
Up to 2 master/2 slave SPI
-
3 HPS PLLs
APPLICATIONS
Machine Vision
Test and Measurement
Embedded Instrumentation
Industrial Automation and Control
Industrial Instrumentation
Medical Instrumentation
Closed Loop Motor Control
BENEFITS
Rapid Development / Deployment
Multiple Connectivity and I/O Options
Rich User Interfaces
High System Integration
High Level OS Support
-
Embedded Linux
-
Micrium uC/OS (via 3
rd
Party)
-
Android (via 3
rd
Party)
-
QNX (via 3
rd
Party)
DESCRIPTION
The MitySOM-5CSx series of highly configurable, small form-factor System-on-Modules
(SoM) feature an Altera Cyclone V System-on-Chip (SoC). Additionally the module
includes on-board power supplies, NOR FLASH and DDR3 RAM memory subsystems. A
MitySOM-5CSx provides a complete and flexible CPU infrastructure for highly integrated
embedded systems.
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Copyright © 2014, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
MitySOM
MitySOM-5CSx System on Module
19 November 2014
The MitySOM-5CSX is available with either a Cyclone V SX or Cyclone V SE which
provide up-to Dual-core Cortex-A9 32-bit RISC processors with dual NEON SIMD
coprocessors. This MPU is capable of running a rich set of real-time operating systems
containing software applications programming interfaces (APIs) expected by modern
system designers. The ARM architecture supports several operating systems, including
Linux, Micrium uC/OS, Android and QNX.
MitySOM 5CSx System On Module Block Diagram
Up To
512 MB
DDR3 RAM
x8
Up To
512 MB
DDR3 RAM
x8
Up To
512 MB
DDR3 RAM
x8
Up To
512 MB
DDR3 RAM
x8
Up To
512 MB
DDR3 RAM
X8
(ECC)
Temperature
(LM73)
RGB LED
(LP5562)
16Kb
EEPROM
HPS DDR3 Interface (Maximum 32 bits wide + 8 bits ECC)
RTC
(AB1803)
I
2
C0
Power Supply
Generation
And
Sequencing
Altera
Cyclone V
SX
w/ 6x 3.125Gbps Xcvrs
or
Cyclone V
SE
w/o Xcvrs
Up-to
133
User FPGA I/O or
107
User FPGA I/O with FPGA DDR
44 User HPS I/O
Up-to DUAL ARM Cortex A9
925 MHz
FPGA Fabric + High Speed Interconnect
26
28
QUAD SPI
QUAD SPI
Boot FLASH NOR FLASH
16 MB NOR Up-to 32 MB
JTAG Connector
(HPS & FPGA)
Up-to 512 MB
DDR3 RAM
X8
(optional)
RGMII1 / NAND / GPIOs
HPS GPI ID
Cyclone V SX only
6 TX, 6 RX, 2 RefClk,
3.125Gbps
USB1
10
2
16
12
14
5
3
8
68
32
6
1
Bank3A/5A FPGA I/O
(Expanded IO
No FPGA DDR)
Bank3B FPGA I/O
Bank8A FPGA I/O
+5VIN
+1.8V
+VIO_EN_2.5V
Bank4A FPGA I/O
Bank5A FPGA I/O
HPS CLK/RESET
USB OTG PHY
FPGA CONFIG
SDMMC/USB0
UART0 TX/RX
CAN/I2C/SPI
MSEL
OTG USB 1
+3VBAT
+V_B4A
+V_B8A
+V_B3B
5
314-pin Edge Connector
Figure 1 MitySOM-5CSx Block Diagram
Figure 1 provides a top level block diagram of the MitySOM-5CSx processor card. As
shown in the figure, the primary interface to the MitySOM-5CSx is through a 314-Pin
card edge interface. Details of the edge connector interface are included in the Card Edge
Interface Description section.
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Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
MitySOM
MitySOM-5CSx System on Module
19 November 2014
MitySOM-5CSx Onboard Storage
DDR3 Memory – HPS Memory
The MitySOM-5CSx includes one dedicated 40-bit DDR3 memory interface. The
memory interface can be up-to 40-bits wide including 8-bits for ECC. A maximum of
2GB of DDR3 RAM with ECC is supported by the MitySOM-5CSx module.
The standard MitySOM-5CSX includes 1GB of DDR3 RAM with ECC (40-bits wide)
integrated on the module.
The standard MitySOM-5CSE includes 512MB of DDR3 RAM without ECC (16-bits
wide) integrated on the module with options for additional memory configurations.
This HPS DDR3 memory is available for both the HPS (Cortex-A9 ARM core(s)) as well
as the FPGA fabric through either the AXI or Avalon high speed interfaces internal to the
Cyclone V.
See Table 9: Standard Model Numbers for additional details.
DDR3 Memory – FPGA Memory (Optional)
The MitySOM-5CSx modules can also include up to 512MB of DDR3 connected directly
to the Cyclone V FPGA fabric. This memory is exclusively for the use of the FPGA
fabric for buffering and local storage and is available through a high speed, low latency
direct connect.
A total of 26 additional FPGA I/O is available through the card edge connector in models
that do not feature the FPGA DDR3 memory. See Table 9: Standard Model Numbers for
additional details.
HPS-FPGA AXI
The high bandwidth HPS-FPGA AXI bridges provided by Altera in the Cyclone V SoC
allow masters in the FPGA fabric to communicate with slaves in the HPS logic and vice
versa. These bridges can be configured for 32, 64, or 128 bit widths.
For example, designers can instantiate additional memories or peripherals in the FPGA
fabric, and master interfaces belonging to components in the HPS logic can access them.
Designers can also instantiate components such as a Nios® II processor in the FPGA
fabric and their master interfaces can access memories or peripherals in the HPS logic,
including DDR3 Memory – HPS Memory.
3
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
MitySOM
MitySOM-5CSx System on Module
19 November 2014
NOR FLASH
A maximum of 48MB (1 x 16MB and 1 x 32MB) of on-board NOR FLASH memory is
connected to the Cyclone V using a Quad Serial Peripheral Interface (QSPI SS0 and
SS1). This is a reliable flash memory that can be used as a boot media for the module.
Configuration EEPROM
MitySOM-5CSx modules contain a 2048 x 8-bit EEPROM that is used to hold
configuration data for the module. The EEPROM is connected to the Cyclone V using
the I2C0 interface. This EEPROM contains information such as the module type, Serial
Number, and MAC addresses for the Ethernet interface(s).
4
Copyright © 2013, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.CriticalLink.com
MitySOM
MitySOM-5CSx System on Module
19 November 2014
On-board Interfaces
The following on-board interfaces were chosen to provide the most flexibility for end
user applications. As many HPS MUX options as possible were left available for the
user. These interfaces should not be muxed external to the module on other pins.
Console Serial port
The console serial port (UART0) is supported on pins 2 (RX) and 4 (TX) of the 314-Pin
Card Edge Connector with a simple TX/RX interface. By default, the flow control signals
are not enabled but can be added to the console serial interface if desired.
Please reference the Card Edge Pin-Out for specific Cyclone V pin-connections.
I2C0 Interface
The I2C0 peripheral is consumed local to the module. It is used for the Real Time Clock,
Temperature Sensor, Configuration EEPROM, and to control a PWM LED driver for
status and debug.
Table 1: I2C0 Peripherals
Address
1000010
1010XXX
1101001
1001100
Device
AS3668
FT24C16A
AB1803-T3
LM73CIMK-1
Feature
LED Driver for RGB Status LED and a Green LED
16Kbit EEPROM for factory config parameters
Real Time Clock
Temperature sensor
QuadSPI Interface
The QUADSPI peripheral is wired to Bank 7B and is used for the NOR FLASH interface
on the module. Both Slave select 0 and slave select 1 have been utilized for this NOR
memory.
Table 2: QSPI Slave Selects
Slave Select
0
1
Feature
Boot flash
Additional flash
Memory Sizing
128Mb –x4 width - 16MB max
128Mb –x4 width (not populated on 16MB NOR
modules) – 32MB max
USB-2.0 OTG Phy
The USB1 interface of the Cyclone V processor is connected directly to a USB 2.0 OTG
phy on the module itself. Only the necessary USB ID, power and data pins are brought
off the module.
Please see Table 7 for the specific pin locations.
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Copyright © 2013, Critical Link LLC
Specifications Subject to Change
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