DS2502
1Kb Add-Only Memory
BENEFITS AND FEATURES
PIN ASSIGNMENT
TO-92
DS2502
NC
NC
DATA
GND
1
2
3
4
8
7
6
5
NC
NC
NC
NC
•
Easily Add Traceability and Relevant Information to Any
Individual System
o
1k-Bit EPROM with Page-Level Write Protection
and Guaranteed Unique 64-Bit ROM ID Chip for
Absolute Traceability
o
1024 Bits Electrically Programmable Read Only
Memory (EPROM)
o
Unique, Factory-Lasered and Tested
64-Bit Registration Number (8-Bit Family Code +
48-Bit Serial Number + 8-Bit CRC Tester)
o
EPROM Partitioned into Four 256-Bit Pages for
Randomly Accessing Packetized Data
o
Each Memory Page Can Be Permanently Write-
Protected to Prevent Tampering
o
Device is an Add Only Memory Where Additional
Data Can Be Programmed into EPROM Without
Disturbing Existing Data
o
Architecture Allows Software to Patch Data by
Superseding an Old Page in Favor of a Newly
Programmed Page
o
8-Bit Family Code Specifies DS2502
Communications Requirements to Reader
•
Minimalist 1-Wire Interface Lowers Cost and Interface
Complexity
o
Reduces Control, Address, Data, Power, and
Programming Signals to a Single Data Pin
o
Directly Connects to a Single Port Pin of a
Microprocessor and Communicates at up to 16.3kb
Per Second
o
Built-In Multidrop Controller Ensures
Compatibility with Other 1-Wire Net Products
o
Presence Pulse Acknowledges When the Reader
First Applies Voltage
o
Low Cost TO-92, SFN, or 8-Pin SO, SOT-23 (3
Pin), TSOC and WLP Surface Mount Package
•
Wide Voltage and Temperature Operating Ranges
Provide Robust System Performance
o
Reads Over Voltage Range of 2.8V to 6.0V at -
40°C to +85°C
o
Zero Standby Power Required
o
Programs at 11.5V to 12.0V from -40°C
to +50°C
8-PIN SO (150 MIL)
TSOC PACKAGE
GND
DATA
NC
1
2
3
6
5
4
NC
NC
NC
TOP VIEW
GND
DATA
NC
SOT-23 Package
Top View
3
1 2 3
09rr
1
2
BOTTOM VIEW
A
1 = DATA; 2, 3 = GND
“rr” = Revision
WLP, Top View with
Laser Mark, Contacts
Not Visible.
“rrd” = Revision/Date
1A, 1B = DATA
2A, 2B = GND
+09rrd
B
1
2
1
2
SFN PINOUT:
PIN 1: IO
PIN 2: GND
BOTTOM VIEW
SFN (APPROX. 6.0mm x 6.0mm x 0.9mm)
NOTE:
THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL
CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE
INFORMATION, REFER TO
APPLICATION NOTE 4132: ATTACHMENT
METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.
SIDE VIEW
19-5075; Rev 3/15
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DS2502
ORDERING INFORMATION
PART
DS2502+
DS2502+T&R
DS2502G+T&R
DS2502P+
DS2502P+T&R
DS2502R+T&R
DS2502S+
DS2502S+T&R
DS2502X1+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
3 TO-92 (straight leads)
3 TO-92 (formed leads, 2k pieces)
2 SFN (2.5k pieces)
6 TSOC
6 TSOC (4k pieces)
3 SOT-23 (3k pieces)
8 SO
8 SO (2.5k pieces)
4 WLP (10k pieces)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
DESCRIPTION
The DS2502 1Kb Add-Only Memory identifies and stores relevant information about the product to
which it is associated. This lot- or product-specific information can be accessed with minimal interface-
for example, a single port pin of a microcontroller. The DS2502 consists of a factory-lasered registration
number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus
1Kb of EPROM which is user-programmable. The power to program and read the DS2502 is derived
entirely from the 1-Wire
communication line.
Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground
return. The entire device can be programmed and then write-protected if desired. Alternatively, the part
may be programmed multiple times with new data being appended to, but not overwriting, existing data
with each subsequent programming of the device. Note: Individual bits can be changed only from a
logical 1 to a logical 0, never from a logical 0 to a logical 1. A provision is also included for indicating
that a certain page or pages of data are no longer valid and have been replaced with new or updated data
that is now residing at an alternate page address. This page address redirection allows software to patch
data and enhance the flexibility of the device as a stand-alone database. The 48-bit serial number that is
factory-lasered into each DS2502 provides a guaranteed unique identity which allows for absolute
traceability. The familiar TO-92 or SOIC or TSOC packages provide a compact enclosure that allows
standard assembly equipment to handle the device easily for attachment to printed circuit boards or
wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking,
product revision status, and access codes.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2502. The DS2502 has three main data components: 1) 64-bit lasered ROM, 2) 1024-bit EPROM,
and 3) EPROM Status Bytes. The device derives its power for read operations entirely from the 1-Wire
communication line by storing energy on an internal capacitor during periods of time when the signal line
is high and continues to operate off of this “parasite” power source during the low times of the 1-Wire
line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wire
communication occurs at normal voltage levels and then is pulsed momentarily to the programming
voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12
volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever
programming voltages are present on the 1-Wire line a special high voltage detect circuit within the
DS2502 generates an internal logic signal to indicate this condition. The hierarchical structure of the 1-
Wire protocol is shown in Figure 2. The bus master must first provide one of the six ROM Function
Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on
the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
2 of 24
DS2502
the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The
protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function
Command is successfully executed, the memory functions that operate on the EPROM portions of the
DS2502 become accessible and the bus master may issue any one of the five Memory Function
Commands specific to the DS2502 to read or program the various data fields. The protocol for these
Memory Function Commands is described in Figure 5. All data is read and written least significant bit
first.
64-BIT LASERED ROM
Each DS2502 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.
The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).
The 64-bit ROM and ROM Function Control section allow the DS2502 to operate as a 1-Wire device and
follow the 1-Wire protocol detailed in the section “1-Wire Bus System.” The memory functions required
to read and program the EPROM sections of the DS2502 are not accessible until the ROM function
protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 9). The 1-
Wire bus master must first provide one of four ROM function commands: 1) Read ROM, 2) Match ROM,
3) Search ROM, or 4) Skip ROM. After a ROM function sequence has been successfully executed, the
bus master may then provide any one of the memory function commands specific to the DS2502 (Figure
6).
The 1-Wire CRC of the lasered ROM is generated using the polynomial X
8
+ X
5
+ X
4
+ 1. Figure 4
shows a hardware implementation of this CRC generator. Additional information about the Maxim
1-Wire Cyclic Redundancy Check is available in
Application Note 27.
The shift register acting as the
CRC accumulator is initialized to 0. Then starting with the least significant bit of the family code, 1 bit at
a time is shifted in. After the 8
th
bit of the family code has been entered, then the serial number is entered.
After the 48
th
bit of the serial number has been entered, the shift register contains the CRC value. Shifting
in the 8 bits of CRC should return the shift register to all 0s.
DS2502 BLOCK DIAGRAM
Figure 1
PARASITE POWER
1-WIRE BUS
DATA
1-WIRE FUNCTION
CONTROL
64-BIT LASERED
ROM
PROGRAM
VOLTAGE
DETECT
MEMORY
FUNCTION
CONTROL
8-BIT
SCRATCHPAD
8-BIT CRC
GENERATOR
1024-BIT EPROM
(4 PAGES OF 32 BYTES)
EPROM
STATUS BYTES
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DS2502
HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL
Figure 2
64-BIT LASERED ROM
Figure 3
8–Bit CRC Code
MSB
LSB MSB
48–Bit Serial Number
8–Bit Family Code (09h)
LSB MSB
LSB
1-WIRE CRC GENERATOR
Figure 4
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DS2502
1024-BITS EPROM
The memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured as
four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when
programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit
CRC from the DS2502 that confirms proper receipt of the data. If the buffer contents are correct, a
programming voltage should be applied and the byte of data will be written into the selected address in
memory. This process ensures data integrity when programming the memory. The details for reading and
programming the 1024-bit EPROM portion of the DS2502 are given in the Memory Function Commands
section.
EPROM STATUS BYTES
In addition to the 1024 bits of data memory the DS2502 provides 64 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS2502. The first byte of the EPROM Status Memory contain the Write Protect Page
bits which inhibit programming of the corresponding page in the 1024-bit main memory area if the
appropriate write protection bit is programmed. Once a bit has been programmed in the Write Protect
Page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be
read.
The next 4 bytes of the EPROM Status Memory contain the Page Address Redirection Bytes, which
indicate if one or more of the pages of data in the 1024-bit EPROM section have been invalidated and
redirected to the page address contained in the appropriate redirection byte. The hardware of the DS2502
makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes
of Status EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by
programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the
data requires changing or updating, but with space permitting, an entire page of data can be redirected to
another page within the DS2502 by writing the one’s complement of the new page address into the Page
Address Redirection Byte that corresponds to the original (replaced) page.
This architecture allows the user’s software to make a “data patch” to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
If a Page Address Redirection Byte has an FFH value, the data in the main memory that corresponds to
that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the
updated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS2502 are given in the Memory Function Commands section.
MEMORY FUNCTION COMMANDS
The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the
various data fields within the DS2502. The Memory Function Control section, 8-bit scratchpad, and the
Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create
the correct control signals within the device. A 3-byte protocol is issued by the bus master. It is comprised
of a command byte to determine the type of operation and two address bytes to determine the specific
starting byte location within a data field. The command byte indicates if the device is to be read or
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