MT40A1G8WE-075E IT:B TR datasheet, PDF

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MT40A1G8WE-075E IT:B TR: DescriptionDynamic Random Access Memory DDR4 8G 1GX8 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size12MB，384 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT40A1G8WE-075E IT:B TR Overview

Dynamic Random Access Memory DDR4 8G 1GX8 FBGA

MT40A1G8WE-075E IT:B TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM - DDR4
Data bus width	8 bit
organize	1 G x 8
Package/box	FBGA-78
storage	8 Gbit
maximum clock frequency	1333 MHz
Supply voltage - max.	1.26 V
Supply voltage - min.	1.14 V
Supply current—max.	76 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 95 C
series	MT40A
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	2000

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4Gb: x4, x8, x16 DDR4 SDRAM

Features

DDR4 SDRAM

MT40A1G4

MT40A512M8

MT40A256M16

Features

•

= V

DDQ

= 1.2V ±60mV

= 2.5V, –125mV/+250mV

On-die, internal, adjustable V

REFDQ

generation

1.2V pseudo open-drain I/O

maximum up to 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

16 internal banks (x4, x8): 4 groups of 4 banks each

8 internal banks (x16): 2 groups of 4 banks each

8n-bit prefetch architecture

Programmable data strobe preambles

Data strobe preamble training

Command/Address latency (CAL)

Multipurpose register READ and WRITE capability

Write leveling

Self refresh mode

Low-power auto self refresh (LPASR)

Temperature controlled refresh (TCR)

Fine granularity refresh

Self refresh abort

Maximum power saving

Output driver calibration

Nominal, park, and dynamic on-die termination

(ODT)

Data bus inversion (DBI) for data bus

Command/Address (CA) parity

Databus write cyclic redundancy check (CRC)

Per-DRAM addressability

Connectivity test

sPPR and hPPR capability

JEDEC JESD-79-4 compliant

Options

• Configuration

– 1 Gig x 4

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (9mm x 11.5mm) – Rev. A

– 78-ball (9mm x 10.5mm) – Rev. B

– 78-ball (8mm x 12mm) – Rev. E

– 78-ball (7.5mm x 11mm) – Rev. F

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) – Rev. A

– 96-ball (9mm x 14mm) – Rev. B

– 96-ball (7.5mm x 13.5mm) – Rev. E, F

• Timing – cycle time

– 0.625ns @ CL = 22 (DDR4-3200)

– 0.682ns @ CL = 20 (DDR4-2933)

– 0.682ns @ CL = 21 (DDR4-2933)

– 0.750ns @ CL = 18 (DDR4-2666)

– 0.750ns @ CL = 19 (DDR4-2666)

– 0.833ns @ CL = 16 (DDR4-2400)

– 0.833ns @ CL = 17 (DDR4-2400)

– 0.937ns @ CL = 15 (DDR4-2133)

– 0.937ns @ CL = 16 (DDR4-2133)

– 1.071ns @ CL = 13 (DDR4-1866)

• Operating temperature

– Commercial (0° T

95°C)

– Industrial (–40° T

95°C)

– Revision

Marking

1G4

512M8

256M16

-062E

-068E

-068

-075E

-075

-083E

-083

-093E

-093

-107E

None

•

Notes:

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on

http://www.micron.com

for available offerings.

2. Not available on Rev. A.

3. Restricted and limited availability.

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x4, x8, x16 DDR4 SDRAM

Features

Contents

Important Notes and Warnings .......................................................................................................................

General Notes and Description .......................................................................................................................

Description ................................................................................................................................................

Industrial Temperature ...............................................................................................................................

General Notes ............................................................................................................................................

Definitions of the Device-Pin Signal Level ...................................................................................................

Definitions of the Bus Signal Level ...............................................................................................................

Functional Block Diagrams .............................................................................................................................

Ball Assignments ............................................................................................................................................

Ball Descriptions ............................................................................................................................................

Package Dimensions .......................................................................................................................................

State Diagram ................................................................................................................................................

Functional Description ...................................................................................................................................

RESET and Initialization Procedure .................................................................................................................

Power-Up and Initialization Sequence .........................................................................................................

RESET Initialization with Stable Power Sequence .........................................................................................

Uncontrolled Power-Down Sequence ..........................................................................................................

Programming Mode Registers .........................................................................................................................

Mode Register 0 ..............................................................................................................................................

Burst Length, Type, and Order .....................................................................................................................

CAS Latency ...............................................................................................................................................

Test Mode ..................................................................................................................................................

Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................

DLL RESET .................................................................................................................................................

Mode Register 1 ..............................................................................................................................................

DLL Enable/DLL Disable ............................................................................................................................

Output Driver Impedance Control ...............................................................................................................

ODT R

TT(NOM)

Values ..................................................................................................................................

Additive Latency .........................................................................................................................................

DQ RX EQ ..................................................................................................................................................

Write Leveling ............................................................................................................................................

Output Disable ...........................................................................................................................................

Termination Data Strobe .............................................................................................................................

Mode Register 2 ..............................................................................................................................................

CAS WRITE Latency ....................................................................................................................................

Low-Power Auto Self Refresh .......................................................................................................................

Dynamic ODT ............................................................................................................................................

Write Cyclic Redundancy Check Data Bus ....................................................................................................

Mode Register 3 ..............................................................................................................................................

Multipurpose Register ................................................................................................................................

WRITE Command Latency When CRC/DM is Enabled .................................................................................

Fine Granularity Refresh Mode ....................................................................................................................

Temperature Sensor Status .........................................................................................................................

Per-DRAM Addressability ...........................................................................................................................

Gear-Down Mode .......................................................................................................................................

Mode Register 4 ..............................................................................................................................................

Hard Post Package Repair Mode ..................................................................................................................

Soft Post Package Repair Mode ....................................................................................................................

WRITE Preamble ........................................................................................................................................

READ Preamble ..........................................................................................................................................

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR4 SDRAM

Features

READ Preamble Training ............................................................................................................................ 63

Temperature-Controlled Refresh ................................................................................................................. 63

Command Address Latency ........................................................................................................................ 63

Internal V

REF

Monitor ................................................................................................................................. 63

Maximum Power Savings Mode ................................................................................................................... 64

Mode Register 5 .............................................................................................................................................. 65

Data Bus Inversion ..................................................................................................................................... 66

Data Mask .................................................................................................................................................. 67

CA Parity Persistent Error Mode .................................................................................................................. 67

ODT Input Buffer for Power-Down .............................................................................................................. 67

CA Parity Error Status ................................................................................................................................. 67

CRC Error Status ......................................................................................................................................... 67

CA Parity Latency Mode .............................................................................................................................. 67

Mode Register 6 .............................................................................................................................................. 68

CCD_L Programming ................................................................................................................................. 69

REFDQ

Calibration Enable .......................................................................................................................... 69

REFDQ

Calibration Range ........................................................................................................................... 69

REFDQ

Calibration Value ............................................................................................................................ 70

DQ RX EQ .................................................................................................................................................. 70

Truth Tables ................................................................................................................................................... 71

NOP Command .............................................................................................................................................. 74

DESELECT Command .................................................................................................................................... 74

DLL-Off Mode ................................................................................................................................................ 74

DLL-On/Off Switching Procedures .................................................................................................................. 76

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 76

DLL-Off to DLL-On Procedure .................................................................................................................... 78

Input Clock Frequency Change ....................................................................................................................... 79

Write Leveling ................................................................................................................................................ 80

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 81

Procedure Description ................................................................................................................................ 82

Write Leveling Mode Exit ............................................................................................................................ 83

Command Address Latency ............................................................................................................................ 85

Low-Power Auto Self Refresh Mode ................................................................................................................. 90

Manual Self Refresh Mode .......................................................................................................................... 90

Multipurpose Register .................................................................................................................................... 92

MPR Reads ................................................................................................................................................. 93

MPR Readout Format ................................................................................................................................. 95

MPR Readout Serial Format ........................................................................................................................ 95

MPR Readout Parallel Format ..................................................................................................................... 96

MPR Readout Staggered Format .................................................................................................................. 97

MPR READ Waveforms ............................................................................................................................... 98

MPR Writes ............................................................................................................................................... 100

MPR WRITE Waveforms ............................................................................................................................. 101

MPR REFRESH Waveforms ........................................................................................................................ 102

Gear-Down Mode .......................................................................................................................................... 105

Maximum Power-Saving Mode ....................................................................................................................... 108

Maximum Power-Saving Mode Entry .......................................................................................................... 108

Maximum Power-Saving Mode Entry in PDA .............................................................................................. 109

CKE Transition During Maximum Power-Saving Mode ................................................................................ 109

Maximum Power-Saving Mode Exit ............................................................................................................ 109

Command/Address Parity .............................................................................................................................. 111

Per-DRAM Addressability .............................................................................................................................. 119

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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