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MT40A1G8WE-083E IT:B TR

Description
Dynamic Random Access Memory DDR4 8G 1GX8 FBGA
Categorysemiconductor    Memory IC    Dynamic random access memory   
File Size12MB,384 Pages
ManufacturerMicron
Websitehttp://www.micron.com/
Environmental Compliance
Download Datasheet Parametric View All

MT40A1G8WE-083E IT:B TR Overview

Dynamic Random Access Memory DDR4 8G 1GX8 FBGA

MT40A1G8WE-083E IT:B TR Parametric

Parameter NameAttribute value
MakerMicron
Product Categorydynamic random access memory
typeSDRAM - DDR4
Data bus width8 bit
organize1 G x 8
Package/boxFBGA-78
storage8 Gbit
maximum clock frequency1200 MHz
Supply voltage - max.1.26 V
Supply voltage - min.1.14 V
Supply current—max.68 mA
Minimum operating temperature- 40 C
Maximum operating temperature+ 95 C
seriesMT40A
EncapsulationReel
Installation styleSMD/SMT
Factory packaging quantity2000
4Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A1G4
MT40A512M8
MT40A256M16
Features
V
DD
= V
DDQ
= 1.2V ±60mV
V
PP
= 2.5V, –125mV/+250mV
On-die, internal, adjustable V
REFDQ
generation
1.2V pseudo open-drain I/O
T
C
maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
sPPR and hPPR capability
JEDEC JESD-79-4 compliant
Options
1
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (9mm x 11.5mm) – Rev. A
– 78-ball (9mm x 10.5mm) – Rev. B
– 78-ball (8mm x 12mm) – Rev. E
– 78-ball (7.5mm x 11mm) – Rev. F
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) – Rev. A
– 96-ball (9mm x 14mm) – Rev. B
– 96-ball (7.5mm x 13.5mm) – Rev. E, F
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.682ns @ CL = 20 (DDR4-2933)
– 0.682ns @ CL = 21 (DDR4-2933)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.750ns @ CL = 19 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
– 1.071ns @ CL = 13 (DDR4-1866)
• Operating temperature
– Commercial (0° T
C
95°C)
– Industrial (–40° T
C
95°C)
– Revision
Marking
1G4
512M8
256M16
2
HX
RH
WE
SA
HA
GE
LY
-062E
-068E
-068
-075E
-075
-083E
-083
-093E
-093
-107E
None
IT
:A
:B
:E
:F
Notes:
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
2. Not available on Rev. A.
3. Restricted and limited availability.
CCMTD-1725822587-9046
4gb_ddr4_dram.pdf - Rev. K 06/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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