16Gb: x4, x8 TwinDie DDR4 SDRAM
Description
TwinDie™ 1.2V DDR4 SDRAM
MT40A4G4 – 128 Meg x 4 x 16 Banks x 2 Ranks
MT40A2G8 – 64 Meg x 8 x 16 Banks x 2 Ranks
Description
The 16Gb (TwinDie™) DDR4 SDRAM uses
Micron’s 8Gb DDR4 SDRAM die (essentially two ranks
of the 8Gb DDR4 SDRAM). Refer to Micron’s 8Gb
DDR4 SDRAM data sheet for the specifications not in-
cluded in this document. Specifications for base part
number MT40A2G4 correlate to TwinDie manufactur-
ing part number MT40A4G4; specifications for base
part number MT40A1G8 correlate to TwinDie manu-
facturing part number MT40A2G8.
Options
• Configuration
– 128 Meg x 4 x 16 banks x 2 ranks
– 64 Meg x 8 x 16 banks x 2 ranks
• FBGA package (Pb-free)
– 78-ball FBGA
(9.5mm x 13mm x 1.2mm) Die Rev :A
– 78-ball FBGA
(8.0mm x 12mm x 1.2mm) Die Rev :B
• Timing – cycle time
1
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
– 0.833ns @ CL = 17 (DDR4-2400)
– 0.937ns @ CL = 15 (DDR4-2133)
– 0.937ns @ CL = 16 (DDR4-2133)
• Self refresh
– Standard
• Operating temperature
– Commercial (0°C
≤
T
C
≤
95°C)
• Revision
Note:
1. CL = CAS (READ) latency.
Marking
4G4
2G8
FSE
NRE
-075E
-083E
-083
-093E
-093
None
None
:A
:B
Features
• Uses 8Gb Micron die
• Two ranks (includes dual CS#, ODT, and CKE balls)
• Each rank has 4 groups of 4 internal banks for con-
current operation
• V
DD
= V
DDQ
= 1.2V (1.14–1.26V)
• 1.2V V
DDQ
-terminated I/O
• JEDEC-standard ball-out
• Low-profile package
• T
C
of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Table 1: Key Timing Parameters
Speed Grade
-075E
-075
-083E
-083
-093E
-093
Note:
1
Data Rate
(MT/s)
2666
2666
2400
2400
2133
2133
Target
t
RCD-
t
RP-CL
18-18-18
19-19-19
16-16-16
17-17-17
15-15-15
16-16-16
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
13.50
14.25
13.32
14.16 (13.75)
14.06 (13.50)
15.00
1. Refer to the Speed Bin Tables for additional details.
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Description
Table 2: Addressing
Parameter
Configuration
Bank group address
Bank count per group
Bank address in bank group
Row address
Column address
4096 Meg x 4
128 Meg x 4 x 16 banks x 2 ranks
BG[1:0]
4
BA[1:0]
128K A[16:0]
1K A[9:0]
2048 Meg x 8
64 Meg x 8 x 16 banks x 2 ranks
BG[1:0]
4
BA[1:0]
64K A[15:0]
1K A[9:0]
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications.
Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications.
Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility.
Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty.
In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA Ball Assignments (Top View)
1
A
V
DD
B
V
PP
C
V
DDQ
D
V
SSQ
E
V
SS
F
V
DD
G
V
SS
H
V
DD
J
V
REFCA
K
V
SS
L
RESET_n
M
V
DD
N
V
SS
Notes:
2
3
4
5
6
7
8
9
A
V
SSQ
V
DDQ
DQ0
NF, NF/
TDQS_c
NF, NF/DM_n/
DBI_n/TDQS_t
V
SSQ
V
DDQ
V
SS
V
SSQ
B
ZQ
C
DQS_c
DQ1
DQS_t
V
DD
DQ3
V
DDQ
D
V
SSQ
E
V
SS
F
V
DD
G
DQ4/NF
DQ2
DQ5/NF
V
DDQ
DQ6/NF
DQ7/NF
V
DDQ
CK_c
C2/ODT1 ODT
CK_t
C0/CKE1
CKE
CS_n
C1/CS1_n RFU/TEN
H
WE_n/A14 ACT_n
CAS_n/A15 RAS_n/A16
V
SS
J
V
DD
K
V
SS
L
ALERT_n
M
BG0
A10/AP
A12/BC_n BG1
BA0
A4
A3
BA1
A6
A0
A1
A5
A8
A2
A9
A7
V
PP
N
V
DD
A11
PAR
A17/NC
A13
1. See the FBGA 78-Ball Descriptions table.
2. Dark balls (with ring) designate balls that are specific to controlling the second die of
the TwinDie package when compared to a monolithic package.
3. A comma “,” separates the configuration; a slash “/” defines a selectable function. For
example: Ball A7 = NF, NF/DM_n/DBI_n/TDQS_t where NF applies to the x4 configuration
only. NF/DM_n/DBI_n/TDQS_t applies to the x8 configuration only and is selectable be-
tween NF, DM_n, DBI_n, or TDQS_t via MRS.
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8 TwinDie DDR4 SDRAM
Ball Assignments and Descriptions
Table 3: FBGA 78-Ball Descriptions
Symbol
A[17:0]
Type
Input
Description
Address inputs:
Provide the row address for ACTIVATE commands and the col-
umn address for READ/WRITE commands to select one location out of the memo-
ry array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/
A16, have additional functions; see individual entries in this table). The address
inputs also provide the op-code during the MODE REGISTER SET command. A16 is
used on some 8Gb and 16Gb parts, and A17 is only used on some 16Gb parts.
Auto precharge:
A10 is sampled during READ and WRITE commands to deter-
mine whether auto precharge should be performed to the accessed bank after a
READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge).
A10 is sampled during a PRECHARGE command to determine whether the PRE-
CHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one
bank is to be precharged, the bank is selected by the bank group and bank ad-
dresses.
Burst chop:
A12/BC_n is sampled during READ and WRITE commands to deter-
mine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW =
burst-chopped). See the Command Truth Table.
Command input:
ACT_n indicates an ACTIVATE command. When ACT_n (along
with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are trea-
ted as row address inputs for the ACTIVATE command. When ACT_n is HIGH
(along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14
are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals.
See the Command Truth Table.
Bank address inputs:
Define the bank (within a bank group) to which an ACTI-
VATE, READ, WRITE, or PRECHARGE command is being applied. Also determines
which mode register is to be accessed during a MODE REGISTER SET command.
Bank group address inputs:
Define the bank group to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command. BG[1:0]
are used in the x4 and x8 configurations.
Stack address inputs:
These inputs are used only when devices are stacked;
that is, 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not
used in the x16 configuration). DDR4 will support a traditional dual-die package
(DDP), which uses these three signals for control of the second die (CS1_n, CKE1,
ODT1). DDR4 is not expected to support a traditional quad-die package (QDP).
For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-
load (master/slave) type of configuration where C0, C1, and C2 are used as chip
ID selects in conjunction with a single CS_n, CKE, and ODT.
Clock:
Differential clock inputs. All address, command, and control input signals
are sampled on the crossing of the positive edge of CK_t and the negative edge
of CK_c.
A10/AP
Input
A12/BC_n
Input
ACT_n
Input
BA[1:0]
Input
BG[1:0]
Input
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
CK_t,
CK_c
Input
PDF: CCMTD-1725822587-6665
16Gb_x4_x8_2cs_TwinDie.pdf - Rev. F 06/18 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2015 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
EEWORLD
