ABRIDGED DATA SHEET
DS2432
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
FEATURES
1128 Bits of 5V EEPROM Memory
Partitioned Into Four Pages of 256 Bits, a
64-Bit Write-Only Secret, and Up to Five
General-Purpose Read/Write Registers
On-Chip 512-Bit ISO/IEC 10118-3 SHA-1
Engine to Compute 160-Bit Message
Authentication Codes (MACs) and to
Generate Secrets
Write Access Requires Knowledge of the
Secret and the Capability of Computing and
Transmitting
a
160-Bit
MAC
as
Authorization
Secret and Data Memory Can Be Write
Protected (All or Page 0 Only) or Put in
EPROM-Emulation Mode (“Write to 0”,
Page 1)
Unique, Factory-Lasered and Tested 64-Bit
Registration Number Assures Absolute
Traceability Because No Two Parts Are Alike
Built-In Multidrop Controller Ensures
Compatibility with Other 1-Wire
®
Net
Products
Reduces Control, Address, Data, and Power
to a Single Data Pin
Directly Connects to a Single Port Pin of a
Microprocessor and Communicates at Up to
15.3kbps
Overdrive Mode Boosts Communication
Speed to 90.9kbps
Low-Cost 6-Lead TSOC Surface-Mount
Package or Solder-Bumped UCSP™ Package
Reads and Writes Over a Wide Voltage
Range of 2.8V to 5.25V from -40°C to +85°C
PIN CONFIGURATIONS
TOP VIEW
GND 1
1-Wire 2
NC 3
TSOC
(150 mils)
6 NC
5 NC
4 NC
A1 MARK
A
B
C
1
DS2432
yywwrr
###xx
2
3
4
UCSP
(TOP VIEW WITH LASER
MARK, CONTACTS NOT
VISIBLE)
A2 = 1-WIRE
A3 = GND
ALL OTHER BUMPS: NC
yywwrr = DATE/REVISION
###xx = LOT NUMBER
REFER TO THE PACKAGE RELIABILITY REPORT FOR
IMPORTANT GUIDELINES ON QUALIFIED USAGE CONDITIONS.
ORDERING INFORMATION
PART
DS2432P+
DS2432P+T&R
DS2432X-S+
TEMP
RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
6 TSOC
6 TSOC
8 UCSP (2.5k
-40°C to +85°C
pcs, T&R)
+Denotes
a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Request Full Data Sheet at:
www.maximintegrated.com/DS2432
1-Wire is a registered trademark and UCSP is a trademark of Maxim Integrated Products, Inc.
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219-0003; Rev 9/12
ABRIDGED DATA SHEET
DS2432
DESCRIPTION
The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to
five user read/write bytes, a 512-bit SHA-1 engine, and a fully-featured 1-Wire interface in a single chip.
Each DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide
a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. The DS2432 has an additional memory area
called the scratchpad that acts as a buffer when writing to the main memory, the register page or when
installing a new secret. Data is first written to the scratchpad from where it can be read back. After the
data has been verified, a copy scratchpad command will transfer the data to its final memory location,
provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the
secret and additional data stored in the DS2432 including the device’s registration number. Only a new
secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute
160-bit message authentication codes (MAC) when reading a memory page or to compute a new secret,
instead of loading it. Applications of the DS2432 include intellectual property security, after-market
management of consumables, and tamper-proof data carriers.
OVERVIEW
The block diagram in Figure 1 shows the relationships between the major control and memory sections of
the DS2432. The DS2432 has five main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3)
four 32-byte pages of EEPROM, 4) 64-bit register page, 5) 64-bit Secrets Memory, and 6) a 512-bit
SHA-1 Engine (SHA = Secure Hash Algorithm). The hierarchical structure of the 1-Wire protocol is
shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1)
Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-
Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte
executed at regular speed, the device will enter Overdrive mode where all subsequent communication
occurs at a higher speed. The protocol required for these ROM function commands is described in Figure
9. After a ROM function command is successfully executed, the memory and SHA-1 functions become
accessible and the master may provide any one of the seven memory function commands. The protocol
for these memory function commands is described in Figure 7
*
.
All data is read and written least
significant bit first.
*
For Figure 7, refer to the full version of the data sheet.
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ABRIDGED DATA SHEET
DS2432
DS2432 BLOCK DIAGRAM
Figure 1
PARASITE POWER
1-Wire net
1-Wire
Function Control
64-bit
Lasered ROM
Memory and
SHA-1 Function
Control Unit
512-bit
Secure Hash
Algorithm
Engine
CRC-16
Generator
64-bit
Scratchpad
Data Memory
4 Pages of
256 bits each
Register Page
64 bits
Secrets Memory
64 bits
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ABRIDGED DATA SHEET
DS2432
Each DS2432 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See
Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information about the
1-Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are
initialized to zero. Then starting with the least significant bit of the family code, one bit at a time is
shifted in. After the 8
th
bit of the family code has been entered, then the serial number is entered. After the
48
th
bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the
eight bits of CRC should return the shift register to all zeros.
64-BIT LASERED ROM
HIERARCHCAL STRUCTURE FOR 1-Wire PROTOCOL
Figure 2
BUS
Master
1-Wire net
Other
Devices
DS2432
Command
Level:
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
1-Wire ROM Function
Commands (see Figure 9)
DS2432-specific
Memory Function
Commands (see Figure 7)
For details see the full
version of the data sheet.
64-BIT LASERED ROM
Figure 3
MSB
8-Bit CRC Code
MSB
LSB
MSB
48-Bit Serial Number
LSB
LSB
8-Bit Family Code
*
MSB
LSB
*
For the actual Family Code value, refer to the full version of the data sheet.
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ABRIDGED DATA SHEET
DS2432
1-Wire CRC GENERATOR
Figure 4
Polynomial = X + X + X + 1
8
5
4
1
STAGE
st
2
STAGE
nd
3
STAGE
rd
4
STAGE
th
5
STAGE
th
6
STAGE
th
7
STAGE
th
8
STAGE
th
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
INPUT DATA
MEMORY MAP
The DS2432 has four memory areas: data memory, secrets memory, register page with special function
registers and user-bytes, and a scratchpad. The data memory is organized in pages of 32 bytes. Secret,
register page and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data
memory, loading the initial secret or when writing to the register page. For further details (including
Figure 5) refer to the full version of the data sheet.
ADDRESS REGISTERS AND TRANSFER STATUS
The DS2432 employs three address registers: TA1, TA2 and E/S (Figure 6). These registers are common
to many other 1-Wire devices but operate slightly differently with the DS2432. Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data will be read.
Register E/S is a read-only transfer-status register, used to verify data integrity with write commands.
Since the scratchpad of the DS2432 is designed to accept data in blocks of eight bytes only, the lower
three bits of TA1 will be forced to 0 and the lower three bits of the E/S register (Ending Offset) will
always read 1. This indicates that all the data in the scratchpad will be used for a subsequent copying into
main memory or secret. Bit 5 of the E/S register, called PF or “partial byte flag”, is a logic-1 if the
number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not
valid due to a loss of power. A valid write to the scratchpad will clear the PF bit. Bits 3, 4 and 6 have no
function; they always read 1. The Partial Flag supports the master checking the data integrity after a
Write command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as
a flag to indicate that the data stored in the scratchpad has already been copied to the target memory
address. Writing data to the scratchpad clears this flag.
ADDRESS REGISTERS
Figure 6
Bit #
Target Address (TA1)
Target Address (TA2)
Ending Address with
Data Status (E/S)
(Read Only)
7
T7
T15
AA
6
T6
T14
1
5
T5
T13
PF
4
T4
T12
1
3
T3
T11
1
2
T2
(0)
T10
E2
(1)
1
T1
(0)
T9
E1
(1)
0
T0
(0)
T8
E0
(1)
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