R1LV0408D Series
4M SRAM (512-kword
×
8-bit)
REJ03C0310-0100
Rev.1.00
May.24.2007
Description
The R1LV0408D is a 4-Mbit static RAM organized 512-kword
×
8-bit, fabricated by Renesas’s high-
performance 0.15µm CMOS and TFT technologies. R1LV0408D Series has realized higher density,
higher performance and low power consumption. The R1LV0408D Series offers low power standby
power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-
pin TSOP II and 32-pin STSOP.
Features
•
Single 3 V supply: 2.7 V to 3.6 V
•
Access time: 55/70 ns (max)
•
Power dissipation:
Standby: 3
µW
(typ)
•
Equal access and cycle times
•
Common data input and output.
Three state output
•
Directly TTL compatible.
All inputs and outputs
•
Battery backup operation.
Rev.1.00, May.24.2007, page 1 of 12
R1LV0408D Series
Ordering Information
Type No.
R1LV0408DSP-5S%
R1LV0408DSP-7L%
R1LV0408DSB-5S%
R1LV0408DSB-7L%
R1LV0408DSA-5S%
R1LV0408DSA-7L%
Access time
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
8mm
×
13.4mm STSOP (32P3K-B)
400-mil 32-pin plastic TSOP II (32P3Y-H)
Package
525-mil 32-pin plastic SOP (32P2M-A)
%:
Temperature version; see table below.
%
R
I
Temperature Range
0 to +70°C
−40
to +85°C
Rev.1.00, May.24.2007, page 2 of 12
R1LV0408D Series
Pin Arrangement
32-pin SOP
32-pin TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
32-pin STSOP
A11
A9
A8
A13
WE#
A18
A15
V
CC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS# (CS)
OE# (OE)
WE# (WE)
V
CC
V
SS
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
Rev.1.00, May.24.2007, page 3 of 12
R1LV0408D Series
Block Diagram
LSB
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
V
CC
V
SS
•
•
•
•
•
Row
Decoder
Memory Matrix
2,048
×
2,048
MSB
I/O0
Input
Data
Control
I/O7
•
•
Column I/O
Column Decoder
•
•
LSB A0 A1 A2 A3 A4 A5 A17 A18 MSB
•
•
CS#
WE#
OE#
Timing Pulse Generator
Read/Write Control
Rev.1.00, May.24.2007, page 4 of 12
R1LV0408D Series
Operation Table
WE#
×
H
H
L
L
CS#
H
L
L
L
L
OE#
×
H
L
H
L
Mode
Not selected
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
I/O0 to I/O7
High-Z
High-Z
Dout
Din
Din
Ref. cycle
Read cycle
Write cycle (1)
Write cycle (2)
Note: H: V
IH
, L: V
IL
,
×:
V
IH
or V
IL
Absolute Maximum Ratings
Parameter
Power supply voltage relative to V
SS
Terminal voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Symbol
V
CC
V
T
P
T
Topr
R ver.
I ver.
Storage temperature range
Storage temperature range under bias
Tstg
Tbias
R ver.
I ver.
Notes: 1. V
T
min:
−3.0
V for pulse half-width
≤
30 ns.
2. Maximum voltage is +4.6 V.
Value
−0.5
to +4.6
−0.5*
1
to V
CC
+ 0.5*
2
0.7
0 to +70
−40
to +85
−65
to +150
0 to +70
−40
to +85
°C
°C
Unit
V
V
W
°C
DC Operating Conditions
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Ambient temperature range
Note:
R ver.
I ver.
1. V
IL
min:
−3.0
V for pulse half-width
≤
30 ns.
V
IH
V
IL
Ta
Min
2.7
0
2.2
−0.3*
1
0
−40
Typ
3.0
0
Max
3.6
0
V
CC
+ 0.3
0.6
+70
+85
Unit
V
V
V
V
°C
Rev.1.00, May.24.2007, page 5 of 12
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