Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -55°C to +125°C
Lead Temperature (soldering, 10s) ................................. +300°C
Lead Temperature (reflow) TO-92 ................................... +250°C
Lead Temperature (reflow) TDFN, TSOC........................
+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TSOC
Junction-to-Ambient Thermal Resistance (θ
JA
) ........127°C/W
Junction-to-Case Thermal Resistance (θ
JC
) ...............37°C/W
TO-92
Junction-to-Ambient Thermal Resistance (θ
JA
) ........132°C/W
Junction-to-Case Thermal Resistance (θ
JC
) .................4°C/W
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
) ..........55°C/W
Junction-to-Case Thermal Resistance (θ
JC
) .................9°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
(Note 3)
(Note 3, 4)
(Notes 4, 5)
IO pin at V
PUP
(Notes 6, 7, 8)
(Notes 3, 9)
(Notes 6, 7, 10)
(Notes 6, 7, 11)
I
OL
= 4mA
I
OL
= 10mA, 4.75V ≤ V
PUP
≤ 5.25V
Standard speed, R
PUP
= 2200Ω
Recovery Time
(Notes 3, 13)
Rising-Edge Hold-off Time
(Notes 6, 14)
Time Slot Duration
(Notes 3, 15)
t
REC
Overdrive speed, R
PUP
= 2200Ω
Overdrive speed, directly prior to reset
pulse, R
PUP
= 2200Ω
Standard speed
Overdrive speed
Standard speed
Overdrive speed
65
9
5
3
5
1.3
N/A (0)
µs
µs
µs
0.75 x
V
PUP
0.3
0.4
0.5
0.05
3.0
300
1000
1.75
0.65 x
V
PUP
0.5
6.7
5.25
2200
V
Ω
pF
µA
V
V
V
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
REH
t
SLOT
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Maxim Integrated
│
2
DS28E07
1024-Bit, 1-Wire EEPROM
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Reset Low Time
(Note 3)
Presence Detect High
Time
Presence Detect Low Time
Presence-Detect Sample
Time (Notes 3, 16)
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 3, 17)
Write-One Low Time
(Notes 3, 17)
IO PIN: 1-Wire READ
Read Low Time
(Notes 3, 18)
Read Sample Time
(Notes 3, 18)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance)
Data Retention
I
PROG
t
PROG
N
CY
t
DR
(Notes 6, 19)
(Note 20)
T
A
= +85°C (Notes 21, 22)
T
A
= +85°C (Notes 23, 24, 25)
1000
10
1.2
12
mA
ms
—
Years
t
RL
t
MSR
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
0.25
t
RL
+ δ
t
RL
+ δ
15 - δ
2-δ
15
2
µs
µs
t
W0L
t
W1L
Standard speed
Overdrive speed
Standard speed
Overdrive speed
60
6
1
0.25
120
15.5
15
2
µs
µs
SYMBOL
CONDITIONS
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
MIN
480
48
15
2
60
8
60
6
TYP
MAX
640
80
60
6
240
24
75
10
UNITS
IO PIN: 1-Wire RESET, PRESENSE-DETECT CYCLE
t
RSTL
t
PDH
t
PDL
t
MSP
µs
µs
µs
µs
Note 2:
Limits are 100% production tested at T
A
= +25°C and T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are at T
A
= +25°C.
Note 3:
System requirement.
Note 4:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5:
Maximum value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 6:
Guaranteed by design and/or characterization only. Not production tested.
Note 7:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Note 8:
Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9:
The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic-zero level.
Note 10:
Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11:
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic-zero.
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Maxim Integrated
│
3
DS28E07
1024-Bit, 1-Wire EEPROM
Note 13:
Applies to a single device attached to a 1-Wire line.
Note 14:
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Note 15:
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 16:
Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E07 present. The power-up
presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 17:
ε in
Figure 11
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18:
δ in
Figure 11
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 19:
Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to V
PUPMIN
. If V
PUP
in the system is close to V
PUPMIN
, a low
impedance bypass of R
PUP
, which can be activated during programming, may need to be added.
Note 20:
Interval begins t
REHMAX
after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from I
PROG
to I
L
.
Note 21:
Write-cycle endurance is tested in compliance with JESD47G.
Note 22:
Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23:
Data retention is tested in compliance with JESD47G.
Note 24:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated
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