MT46H32M32LFB5-5 IT:B TR datasheet, PDF

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MT46H32M32LFB5-5 IT:B TR: DescriptionDynamic Random Access Memory MOBILE DDR 1G 32MX32 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size6MB，103 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT46H32M32LFB5-5 IT:B TR Overview

Dynamic Random Access Memory MOBILE DDR 1G 32MX32 FBGA

MT46H32M32LFB5-5 IT:B TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM Mobile - LPDDR1
Data bus width	32 bit
organize	32 M x 32
Package/box	VFBGA-90
storage	1 Gbit
maximum clock frequency	200 MHz
interview time	5 ns
Supply voltage - max.	1.95 V
Supply voltage - min.	1.7 V
Supply current—max.	95 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 85 C
series	MT46H
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	1000

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1Gb: x16, x32 Mobile LPDDR SDRAM

Features

Mobile Low-Power DDR SDRAM

MT46H64M16LF – 16 Meg x 16 x 4 banks

MT46H32M32LF – 8 Meg x 32 x 4 banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh, 32ms for automotive temperature

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-54

-6

-75

Clock Rate

200 MHz

185 MHz

166 MHz

133 MHz

Access Time

5.0ns

6.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 64 Meg x 16 (16 Meg x 16 x 4

banks)

– 32 Meg x 32 (8 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• PoP (plastic "green" package)

– 168-ball WFBGA (12mm x 12mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 5.4ns @ CL = 3 (185 MHz)

– 6ns @ CL = 3 (166 MHz)

– 7.5ns @ CL = 3 (133 MHz)

• Power

– Standard I

DD2

DD6

• Operating temperature range

– Commercial (0˚ to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Design revision

Notes:

Marking

64M16

32M32

-5

-54

-6

-75

None

1. Only available for x16 configuration.

2. Only available for x32 configuration.

3. Contact factory for availability.

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. K 10/2018 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb: x16, x32 Mobile LPDDR SDRAM

Features

Contents

Important Notes and Warnings ......................................................................................................................... 9

General Description ....................................................................................................................................... 10

Functional Block Diagrams ............................................................................................................................. 11

Ball Assignments and Descriptions ................................................................................................................. 13

Package Dimensions ....................................................................................................................................... 18

Electrical Specifications .................................................................................................................................. 21

Electrical Specifications – I

Parameters ........................................................................................................ 25

Electrical Specifications – AC Operating Conditions ......................................................................................... 31

Output Drive Characteristics ........................................................................................................................... 36

Functional Description ................................................................................................................................... 39

Commands .................................................................................................................................................... 40

DESELECT ................................................................................................................................................. 41

NO OPERATION ......................................................................................................................................... 41

LOAD MODE REGISTER ............................................................................................................................. 41

ACTIVE ...................................................................................................................................................... 41

READ ......................................................................................................................................................... 42

WRITE ....................................................................................................................................................... 43

PRECHARGE .............................................................................................................................................. 44

BURST TERMINATE ................................................................................................................................... 45

AUTO REFRESH ......................................................................................................................................... 45

SELF REFRESH ........................................................................................................................................... 46

DEEP POWER-DOWN ................................................................................................................................. 46

Truth Tables ................................................................................................................................................... 47

State Diagram ................................................................................................................................................ 52

Initialization .................................................................................................................................................. 53

Standard Mode Register .................................................................................................................................. 56

Burst Length .............................................................................................................................................. 57

Burst Type .................................................................................................................................................. 57

CAS Latency ............................................................................................................................................... 58

Operating Mode ......................................................................................................................................... 59

Extended Mode Register ................................................................................................................................. 60

Temperature-Compensated Self Refresh ...................................................................................................... 60

Partial-Array Self Refresh ............................................................................................................................ 61

Output Drive Strength ................................................................................................................................ 61

Status Read Register ....................................................................................................................................... 62

Bank/Row Activation ...................................................................................................................................... 64

READ Operation ............................................................................................................................................. 65

WRITE Operation ........................................................................................................................................... 76

PRECHARGE Operation .................................................................................................................................. 88

Auto Precharge ............................................................................................................................................... 88

Concurrent Auto Precharge ......................................................................................................................... 89

AUTO REFRESH Operation ............................................................................................................................. 94

SELF REFRESH Operation ............................................................................................................................... 95

Power-Down .................................................................................................................................................. 96

Deep Power-Down ..................................................................................................................................... 98

Clock Change Frequency ............................................................................................................................... 100

Revision History ............................................................................................................................................ 101

Rev. K – 10/18 ............................................................................................................................................ 101

Rev. J – 1/14 ............................................................................................................................................... 101

Rev. I – 10/13 ............................................................................................................................................. 101

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. K 10/2018 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb: x16, x32 Mobile LPDDR SDRAM

Features

List of Figures

Figure 1: 1Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ....................................................................................................... 11

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 12

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 13

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 14

Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 15

Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 18

Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 19

Figure 9: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ....................................................................... 20

Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 30

Figure 11: ACTIVE Command ........................................................................................................................ 42

Figure 12: READ Command ........................................................................................................................... 43

Figure 13: WRITE Command ......................................................................................................................... 44

Figure 14: PRECHARGE Command ................................................................................................................ 45

Figure 15: DEEP POWER-DOWN Command ................................................................................................... 46

Figure 16: Simplified State Diagram ............................................................................................................... 52

Figure 17: Initialize and Load Mode Registers ................................................................................................. 54

Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 55

Figure 19: Standard Mode Register Definition ................................................................................................. 56

Figure 20: CAS Latency .................................................................................................................................. 59

Figure 21: Extended Mode Register ................................................................................................................ 60

Figure 22: Status Read Register Timing ........................................................................................................... 62

Figure 23: Status Register Definition .............................................................................................................. 63

Figure 24: READ Burst ................................................................................................................................... 66

Figure 25: Consecutive READ Bursts .............................................................................................................. 67

Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 68

Figure 27: Random Read Accesses .................................................................................................................. 69

Figure 28: Terminating a READ Burst ............................................................................................................. 70

Figure 29: READ-to-WRITE ............................................................................................................................ 71

Figure 30: READ-to-PRECHARGE .................................................................................................................. 72

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 73

Figure 32: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 74

Figure 33: Data Output Timing –

AC and

DQSCK .......................................................................................... 75

Figure 34: Data Input Timing ......................................................................................................................... 77

Figure 35: Write – DM Operation .................................................................................................................... 78

Figure 36: WRITE Burst ................................................................................................................................. 79

Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 80

Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 80

Figure 39: Random WRITE Cycles .................................................................................................................. 81

Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 82

Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 83

Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 84

Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 85

Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 86

Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 87

Figure 46: Bank Read – With Auto Precharge ................................................................................................... 90

Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 91

Figure 48: Bank Write – With Auto Precharge .................................................................................................. 92

Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 93

Figure 50: Auto Refresh Mode ........................................................................................................................ 94

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. K 10/2018 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT46H32M32LFB5-5 IT:B TR Related Products

	MT46H32M32LFB5-5 IT:B TR	MT46H64M16LFBF-5 IT:B TR	MT46H32M32LFB5-5 IT:B	MT46H64M16LFBF-5 IT:B	MT46H32M32LFT68MWC2	MT46H64M16LFT68MWC2
Description	Dynamic Random Access Memory MOBILE DDR 1G 32MX32 FBGA	Dynamic Random Access Memory MOBILE DDR 1G 64MX16 FBGA	Dynamic Random Access Memory MOBILE DDR 1G 32MX32 FBGA	Dynamic Random Access Memory MOBILE DDR 1G 64MX16 FBGA	Dynamic Random Access Memory MOBILE DDR 1G Die 32MX32	Dynamic Random Access Memory MOBILE DDR 1G Die 64MX16
Maker	Micron	Micron	Micron	Micron	Micron	Micron
Product Category	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory
type	SDRAM Mobile - LPDDR1	SDRAM Mobile - LPDDR1	SDRAM Mobile - LPDDR1	SDRAM Mobile - LPDDR1	SDRAM Mobile - LPDDR1	SDRAM Mobile - LPDDR1
Data bus width	32 bit	16 bit	32 bit	16 bit	32 bit	16 bit
organize	32 M x 32	64 M x 16	32 M x 32	64 M x 16	32 M x 32	64 M x 16
Package/box	VFBGA-90	VFBGA-60	VFBGA-90	VFBGA-60	DIE	DIE
storage	1 Gbit	1 Gbit	1 Gbit	1 Gbit	1 Gbit	1 Gbit
Supply voltage - max.	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Supply voltage - min.	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Minimum operating temperature	- 40 C	- 40 C	- 40 C	- 40 C	0 C	0 C
Maximum operating temperature	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 70 C	+ 70 C
series	MT46H	MT46H	MT46H	MT46H	MT46H	MT46H
Factory packaging quantity	1000	1000	1440	1782	1	1
maximum clock frequency	200 MHz	200 MHz	200 MHz	200 MHz	-	-
interview time	5 ns	5 ns	5 ns	5 ns	-	-
Supply current—max.	95 mA	95 mA	95 mA	95 mA	-	-
Encapsulation	Reel	Reel	Tray	Tray	Tray	Tray
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	-	-

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