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MT41K128M16JT-125 AIT:K TR

Description
Dynamic Random Access Memory DDR3 2G 128MX16 FBGA
Categorysemiconductor    Memory IC    Dynamic random access memory   
File Size3MB,213 Pages
ManufacturerMicron
Websitehttp://www.micron.com/
Environmental Compliance
Download Datasheet Parametric View All

MT41K128M16JT-125 AIT:K TR Overview

Dynamic Random Access Memory DDR3 2G 128MX16 FBGA

MT41K128M16JT-125 AIT:K TR Parametric

Parameter NameAttribute value
MakerMicron
Product Categorydynamic random access memory
typeSDRAM - DDR3L
Data bus width16 bit
organize128 M x 16
Package/boxFBGA-96
storage2 Gbit
Supply voltage - max.1.45 V
Supply voltage - min.1.283 V
Minimum operating temperature- 40 C
Maximum operating temperature+ 95 C
seriesMT41K
EncapsulationCut Tape
EncapsulationMouseReel
EncapsulationReel
Installation styleSMD/SMT
Factory packaging quantity2000
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
1.35V Automotive DDR3L SDRAM
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
Output driver calibration
AEC-Q100
2
PPAP submission
8D response time
Options
• Configuration
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free)
– 78-ball FBGA (8mm x 10.5mm)
– x8
– 96-ball FBGA (8mm x 14mm)
– x16
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40°C T
C
+95°C)
– Automotive (–40°C T
C
+105°C)
– Ultra-high (–40°C T
C
+125°C)
3
• Revision
Notes:
Marking
256M8
128M16
DA
JT
Features
V
DD
= V
DDQ
= 1.35V (1.283–1.45V)
Backward-compatible to V
DD
= V
DDQ
= 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
Refresh maximum interval time at T
C
temperature
range
– 64ms at –40°C to +85°C
– 32ms at +85°C to +105°C
– 16ms at +105°C to +115°C
– 8ms at +115°C to +125°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
-107
-125
-15E
-187E
A
IT
AT
UT
:K
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on
http://www.micron.com for available offer-
ings.
2. Contact Micron sales for AEC-Q100 gap re-
port.
3. The UT option use based on automotive us-
age model. Please contact Micron sales rep-
resentative if you have questions. The UT
option is not available for -107 speed grade.
Table 1: Key Timing Parameters
Speed Grade
-107
1, 2, 3
-125
1, 2
Data Rate (MT/s)
1866
1600
Target
t
RCD-
t
RP-CL
13-13-13
11-11-11
t
RCD
(ns)
t
RP
(ns)
CL (ns)
13.91
13.75
13.91
13.75
13.91
13.75
09005aef85741711
2Gb_auto_DDR3L.pdf - Rev. C 3/18 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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