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MT46V32M16CY-5B IT:J TR

Description
Dynamic Random Access Memory DDR 512M 32MX16 FBGA
Categorysemiconductor    Memory IC    Dynamic random access memory   
File Size2MB,95 Pages
ManufacturerMicron
Websitehttp://www.micron.com/
Environmental Compliance
Download Datasheet Parametric View All

MT46V32M16CY-5B IT:J TR Overview

Dynamic Random Access Memory DDR 512M 32MX16 FBGA

MT46V32M16CY-5B IT:J TR Parametric

Parameter NameAttribute value
MakerMicron
Product Categorydynamic random access memory
typeSDRAM - DDR1
Data bus width16 bit
organize32 M x 16
Package/boxFBGA-60
storage512 Mbit
maximum clock frequency200 MHz
Supply voltage - max.2.7 V
Supply voltage - min.2.5 V
Supply current—max.85 mA
Minimum operating temperature- 40 C
Maximum operating temperature+ 85 C
seriesMT46V
EncapsulationCut Tape
EncapsulationMouseReel
EncapsulationReel
Installation styleSMD/SMT
Factory packaging quantity2000
512Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
Features
• V
DD
= 2.5V ±0.2V, V
DDQ
= 2.5V ±0.2V
V
DD
= 2.6V ±0.1V, V
DDQ
= 2.6V ±0.1V (DDR400)
1
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
(x16 has two – one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh
64ms, 8192-cycle
• Longer-lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
t
RAS lockout supported (
t
RAP =
t
RCD)
Options
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic package
66-pin TSOP
66-pin TSOP (Pb-free)
60-ball FBGA (10mm x 12.5mm)
60-ball FBGA (10mm x 12.5mm) (Pb-free)
60-ball FBGA (8mm x 12.5mm)
60-ball FBGA (8mm x 12.5mm) (Pb-free)
• Timing – cycle time
5ns @ CL = 3 (DDR400)
6ns @ CL = 2.5 (DDR333) (FBGA only)
6ns @ CL = 2.5 (DDR333) (TSOP only)
• Self refresh
Standard
Low-power self refresh
• Temperature rating
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
• Revision
x4, x8, x16
x4, x8, x16
Marking
128M4
64M8
32M16
TG
P
FN
2
BN
2
CV
3
CY
3
-5B
-6
2
-6T
2
None
L
None
IT
:F
:J
Notes: 1. DDR400 devices operating at < DDR333
conditions can use V
DD
/V
DDQ
= 2.5V +0.2V.
2. Available only on Revision F.
3. Available only on Revision J.
Table 1:
Key Timing Parameters
CL = CAS (READ) latency; data-out window is MIN clock rate with 50% duty cycle at CL = 2, CL = 2.5, or CL = 3
Speed
Grade
-5B
-6
6T
-75E/-75Z
-75
Clock Rate (MHz)
CL = 2
133
133
133
133
100
CL = 2.5
167
167
167
133
133
CL = 3
200
n/a
n/a
n/a
n/a
Data-Out
Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
0.40ns
0.40ns
0.45ns
0.50ns
0.50ns
PDF: 09005aef80a1d9d4/Source: 09005aef82a95a3a
512Mb_DDR_x4x8x16_D1.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology, Inc. All rights reserved.
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