Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
)
..........60°C/W
Junction-to-Case Thermal Resistance (θ
JC
)
...............11°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching
Threshold
Input Low Voltage
Low-to-High Switching
Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Time Slot Duration
(Notes 3, 14)
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
SLOT
(Note 3)
V
PUP
= 3.3V ±10% (Note 4)
(Notes 5, 6)
IO pin at V
PUP
(Notes 6, 7, 8)
(Notes 3, 9)
(Notes 6, 7, 10)
(Notes 6, 7, 11)
I
OL
= 4mA (Note 12)
R
PUP
= 750Ω (Notes 3, 13)
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
Standard speed
Overdrive speed
10
65
13
480
48
480
48
60
8
60
8
72
10
120
16
640
80
0.75 x
V
PUP
0.3
0.4
2.97
300
6.5
5
0.65 x
V
PUP
0.3
22
3.63
750
V
Ω
nF
µA
V
V
V
V
V
µs
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time (Note 3)
Reset High Time (Note 15)
Presence Detect Sample Time
(Notes 3, 16)
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 3, 17)
t
W0L
µs
t
RSTL
t
RSTH
t
MSP
µs
µs
µs
www.maximintegrated.com
Maxim Integrated │
2
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Write-One Low Time
(Notes 3, 17)
IO PIN: 1-Wire READ
Read Low Time
(Notes 3, 18)
Read Sample Time
(Notes 3, 18)
MEMORY
Programming Current
Programming Time for a
Memory Block
Data Retention
I
PROG
t
PROG
t
DR
V
PUP
= 3.63V (Notes 6, 19, 20)
(Notes 20, 21)
T
A
= +85°C (Note 22)
10
t
RL
t
MSR
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
t
RL
+
d
t
RL
+
d
15 -
d
2-
d
15
2
12
20
µs
µs
SYMBOL
t
W1L
CONDITIONS
Standard speed
Overdrive speed
MIN
1
1
TYP
MAX
15
2
UNITS
µs
mA
ms
Years
Note 2:
Limits are 100% production tested at T
A
= +25°C or T
A
= +85°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Typical values are at T
A
= +25°C.
Note 3:
System requirement.
Note 4:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5:
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 6:
Guaranteed by design and/or characterization only. Not production tested.
Note 7:
V
TL
, V
TH
, and V
HY
are functions of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values
of V
TL
, V
TH
, and V
HY
.
Note 8:
Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9:
The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic-zero level.
Note 10:
Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11:
After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic-zero.
Note 12:
The I-V characteristic is linear for voltages less than 1V.
Note 13:
Applies to a single device attached to a 1-Wire line.
Note 14:
Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 15:
An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 16:
Interval after t
RSTL
during which a bus master can read a logic-zero on IO if there is a DS28E80 present. The power-up
presence detect pulse can be outside this interval, but it is completed within 2ms after power-up. 1-Wire communication
should be considered invalid until 2ms after power-up. Send a 1-Wire reset after POR for presence detect.
Note 17:
ε in
Figure 10
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 18:
δ in
Figure 10
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 19:
Current drawn from IO during the programming interval. The pullup circuits on IO during the programming interval should
be such that the voltage at IO is greater than or equal to V
PUPMIN
. A low-impedance bypass of R
PUP
, which can be acti-
vated during programming, may need to be added.
Note 20:
T
A
= 0°C to +50°C.
Note 21:
The t
PROG
interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte (FFh) for
a valid Write Block sequence. The interval ends once the device’s self-timed programming cycle is complete and the cur-
rent drawn by the device has returned from I
PROG
to I
L
.
Note 22:
Data retention is tested in compliance with JESD47G. No elevated gamma radiation level.
www.maximintegrated.com
Maxim Integrated │ 3
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Pin Configuration
TOP VIEW
DS28E80
N.C. 1
IO
GND
+
6
4
5
N.C.
N.C.
N.C.
2
3
EP*
TDFN-EP
3mm x 3mm
*EP = EXPOSED PAD
Pin Description
PIN
1, 4–6
2
3
—
NAME
N.C.
IO
GND
EP
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Ground Reference
Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to
Application Note 3273:
Exposed Pads: A Brief Introduction
for additional information.
FUNCTION
Detailed Description
The DS28E80 combines 1984 bits of 8-times program-
mable radiation hard nonvolatile user memory, adminis-
tration memory, protection memory, and a 64-bit ROM ID
in a single chip. A data buffer assists when writing to the
memory. Data is transferred serially through the 1-Wire
protocol that requires only a single data lead and a
ground return. The user memory can be write protected
to prevent overwriting the memory data. The protection
applies to individual memory blocks. To protect against
adverse effects caused by bit errors, the communication
relies on 16-bit CRCs that the DS28E80 generates at
various places in the protocol. The master verifies the
CRC and, when found correct, transmits a release byte
(any value from 00h to FFh) to approve EEPROM pro-
gramming cycle. In case of a CRC error, the master can
abort the communication and start over.
The device’s 64-bit ROM ID can be used to electronically
identify the object in which the DS28E80 is used. The
ROM ID guarantees unique identification and functions as
logical address in a multidrop 1-Wire network environment
where multiple devices reside on a common 1-Wire bus
and operate independently of each other. The main appli-
cation of the DS28E80 is identification and monitoring of
consumables for medical applications.
Overview
The block diagram in
Figure 1
shows the relationships
between the major control and memory sections of the
DS28E80. The device has five main data components:
user memory (31 blocks of 8 bytes), administration mem-
ory, protection memory, 64-bit ROM ID, and a 64-bit data
buffer.
Figure 2
shows the hierarchical structure of the
1-Wire protocol. The bus master must first provide one of
the seven ROM function commands: Read ROM, Match
ROM, Search ROM, Skip ROM, Resume Communication,
Overdrive-Skip ROM and Overdrive-Match ROM. The
protocol required for these ROM function commands is
described in
Figure 8.
After a ROM function command
is successfully executed, the memory functions become
accessible and the master can provide any one of the
5 available memory function commands. The function
protocols are described in
Figure 6.
All data is read and
written least-significant bit first.
www.maximintegrated.com
Maxim Integrated │
4
DS28E80
Gamma Radiation Resistant 1-Wire Memory
PARASITE POWER
1-Wire BUS
1-Wire
FUNCTION CONTROL
64-BIT
ROM ID
MEMORY
FUNCTION CONTROL
ADMINISTRATION
MEMORY
DS28E80
CRC-16
GENERATOR
PROTECTION
MEMORY
USER
MEMORY
WRITE BUFFER
Figure 1. DS28E80 Block Diagram
DS28E80
COMMAND
LEVEL:
AVAILABLE
COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
WRITE BLOCK
DS28E80-SPECIFIC
MEMORY FUNCTION
COMMANDS
READ MEMORY
WRITE PROTECT BLOCK
READ BLOCK PROTECTION
READ REMAINING CYCLES
DATA FIELD
AFFECTED:
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM ID, RC-FLAG, OD-FLAG
USER MEMORY, ADMINISTRATION
MEMORY, PROTECTION
MEMORY, WRITE BUFFER
USER MEMORY
PROTECTION MEMORY
PROTECTION MEMORY
ADMINISTRATION MEMORY
1-Wire ROM
FUNCTION COMMANDS
Figure 2. Hierarchical Structure for 1-Wire Protocol
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