MT35XU02GCBA1G12-0SIT datasheet, PDF

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MT35XU02GCBA1G12-0SIT: DescriptionNOR FlashSPI FLASH NOR SLC 256MX8 TBGA QDP; Categorysemiconductor Memory IC NOR flash memory; File Size200KB，11 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT35XU02GCBA1G12-0SIT Overview

NOR FlashSPI FLASH NOR SLC 256MX8 TBGA QDP

MT35XU02GCBA1G12-0SIT Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	NOR flash memory
series	MT35X
Encapsulation	Tray
Factory packaging quantity	1122

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Preliminary

‡

Xccela™ Flash Memory Data Sheet Brief

Features

Xccela™ Flash Memory Data Sheet Brief

MT35X 1.8/3V, Octal I/O, 4KB/32KB/128KB Sector Erase

Features

• SPI-compatible Xccela™ bus interface

– Octal DDR protocol

– Extended-SPI protocol with octal commands

• Single and double transfer rate (SDR/DDR)

• Clock frequency:

– 166 MHz (MAX) in SDR (166 MB/s) (1.8V)

– 200 MHz (MAX) in DDR (400 MB/s) with DQS

(1.8V)

– 133 MHz (MAX) in SDR (133 MB/s) (3.0V)

– 133 MHz (MAX) in DDR (266MB/s) with DQS

(3.0V)

• Execute-in-place (XIP)

• PROGRAM/ERASE SUSPEND operations

• Volatile and nonvolatile configuration settings

• Software reset

• Reset pin available

• 3-byte and 4-byte address modes – enable memory

access beyond 128Mb

• Dedicated 64-byte OTP area outside main memory

– Readable and user-lockable

– Permanent lock with PROGRAM OTP command

• Erase capability

– Bulk erase for monolithic, die erase for stacked

devices

– Sector erase 128KB uniform granularity

– Subsector erase 4KB, 32KB granularity

• Security and write protection

– Volatile and nonvolatile locking and software

write protection for each 128KB sector

– Nonvolatile configuration locking and password

protection

– Protection management register offering en-

hanced security features

– Hardware write protection: nonvolatile bits

(BP[3:0] and TB) define protected area size

– Program/erase protection during power-up

– CRC detects accidental changes to raw data

• Electronic signature

– JEDEC-standard 3-byte signature

– Extended device ID: two additional bytes identify

device factory options

• JESD47I-compliant

– Minimum 100,000 ERASE cycles per sector

– Data retention: 20 years (TYP)

Options

• Voltage

– 1.7–2.0V

– 2.7–3.6V

• Density

– 256Mb

– 512Mb

– 1Gb

– 2Gb

• Device stacking

– Monolithic

– 2 die stacked

– 4 die stacked

• Device Generation

• Die revision

• Configuration

– Boot in SDR x1

– Boot in DDR x8

• Sector Size

– 128KB

• Packages: JEDEC-standard, RoHS-com-

pliant

– 24-ball T-PBGA 05/6mm x 8mm

(5 x 5 array)

• Security features

– Standard security

• Special options

– Standard

– Automotive

• Operating temperature range

– From –40°C to +85°C

– From –40°C to +105°C

– From –40°C to +125°C

Marking

256

512

01G

02G

CCMTD-1718347970-10442

Xccela_summary– Rev. A 04/18

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Preliminary

Xccela™ Flash Memory Data Sheet Brief

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications.

Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility.

Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

CCMTD-1718347970-10442

Xccela_summary– Rev. A 04/18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Preliminary

Xccela™ Flash Memory Data Sheet Brief

Device Description

This is a brief version of the MT35X data sheet. For complete information, please refer

to the full NDA version.

To request access to the full NDA version of the MT35X data sheet, please contact your

sales representative.

The Micron

Xccela

flash is a high-performance, multiple I/O, SPI-compatible flash

memory device. It features a high-speed, low pin count

Xccela

bus interface with a DDR

clock frequency of up to 200 MHz for 1.8V parts and up to 133 MHz for 3.0 V parts, using

eight I/O signals and a data strobe (DQS pin).

SUSPEND and RESUME commands provide the ability to pause and resume PRO-

GRAM/ERASE operations. Nonvolatile and volatile configuration registers enable re-

spective default and temporary settings such as READ operation dummy clock cycles

and wrap modes, memory protection, output buffer impedance, SPI protocol type and

XIP mode.

Memory is organized as uniform 128KB sectors, 4KB and 32KB subsectors, and 256 byte

pages. The device also includes a 64-byte one-time-programmable (OTP) memory area

that can be permanently locked.

Direct boot in octal DDR protocol provides high performance and ease of use, enabling

communication between the host and flash device without need to configure extended

SPI protocol operations. However, the device still supports both extended SPI and octal

DDR protocols to ensure legacy system support and an easy migration path. The exten-

ded SPI protocol supports address and data transmission on one or eight data lines, de-

pending on the command.

Information in octal DDR protocol is always transmitted by eight data lines on both ris-

ing and falling clock edges. Most legacy x1 SPI commands are supported, but require

only one clock cycle because the command is latched on both the rising and falling

edges of the clock. Address cycles are fixed at 4-byte READ operations from the flash ar-

ray.

The host is not required to drive DQS during the input operation to the memory. The

data input (DQ) to the memory still relies on clock (C) to latch all address and data op-

erations. Most register outputs require dummy clock cycles due to the critical timing

from command decoding. With the help of DQS for data latching, the number of dum-

my clocks is transparent to the host.

CCMTD-1718347970-10442

Xccela_summary– Rev. A 04/18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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