MT25QL02GCBB8E12-0AAT TR datasheet, PDF

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MT25QL02GCBB8E12-0AAT TR: DescriptionNOR FlashSPI FLASH NOR SLC 512MX4 TBGA QDP; Categorysemiconductor Memory IC NOR flash memory; File Size1MB，94 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT25QL02GCBB8E12-0AAT TR Overview

NOR FlashSPI FLASH NOR SLC 512MX4 TBGA QDP

MT25QL02GCBB8E12-0AAT TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	NOR flash memory
Installation style	SMD/SMT
Package/box	T-PBGA-24
series	MT25QL
storage	2 Gbit
maximum clock frequency	166 MHz
Interface Type	SPI
organize	256 M x 8
Timing type	Synchronous
Data bus width	8 bit
Supply voltage - min.	2.7 V
Supply voltage - max.	3.6 V
Supply current—max.	110 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 105 C
Encapsulation	Reel
storage type	NOR
speed	166 MHz
standard	Not Supported
Factory packaging quantity	2000

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2Gb, 3V Multiple I/O Serial Flash Memory

Features

Micron Serial NOR Flash Memory

3V, Multiple I/O, 4KB, 32KB, 64KB Sector Erase

MT25QL02GCBB

Features

•

Stacked device (four 512Mb die)

SPI-compatible serial bus interface

Single and double transfer rate (STR/DTR)

Clock frequency

– 133 MHz (MAX) for all protocols in STR

– 90 MHz (MAX) for all protocols in DTR

Dual/quad I/O commands for increased through-

put up to 90 MB/s

Supported protocols in both STR and DTR

– Extended I/O protocol

– Dual I/O protocol

– Quad I/O protocol

Execute-in-place (XIP)

PROGRAM/ERASE SUSPEND operations

Volatile and nonvolatile configuration settings

Software reset

Additional reset pin for selected part numbers

3-byte and 4-byte address modes: enable memory

access beyond 128Mb

Dedicated 64-byte OTP area outside main memory

– Readable and user-lockable

– Permanent lock with PROGRAM OTP command

Erase capability

– Die erase

– Sector erase 64KB uniform granularity

– Subsector erase 4KB, 32KB granularity

Security and write protection

– Volatile and nonvolatile locking and software

write protection for each 64KB sector

– Nonvolatile configuration locking

– Password protection

– Hardware write protection: nonvolatile bits

(BP[3:0] and TB) define protected area size

– Program/erase protection during power-up

– CRC detects accidental changes to raw data

Electronic signature

– JEDEC-standard 3-byte signature (BA22h)

– Extended device ID: two additional bytes identify

device factory options

JESD47H-compliant

– Minimum 100,000 ERASE cycles per sector

– Data retention: 20 years (TYP)

Options

• Voltage

– 2.7–3.6V

• Density

– 2Gb

• Device stacking

– 4 die stacked

• Device generation

• Die revision

• Pin configuration

– RESET# and HOLD#

• Sector Size

– 64KB

• Packages – JEDEC-standard, RoHS-

compliant

– 24-ball T-PBGA 05/6mm x 8mm

(TBGA24)

• Standard security

• Special options

– Standard

– Automotive

• Operating temperature range

– From –40°C to +85°C

– From –40°C to +105°C

Marking

02G

•

09005aef8661dcd4

mt25q-qlkt-L02-CBB-S-IT.pdf - Rev. F 10/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb, 3V Multiple I/O Serial Flash Memory

Features

Contents

Important Notes and Warnings ......................................................................................................................... 8

Device Description ........................................................................................................................................... 9

Device Logic Diagram ................................................................................................................................. 10

Advanced Security Protection ..................................................................................................................... 10

Signal Assignments – Package Code: 12 ........................................................................................................... 11

Signal Descriptions ......................................................................................................................................... 12

Package Dimensions – Package Code: 12 ......................................................................................................... 13

Memory Map – 2Gb Density ............................................................................................................................ 15

Status Register ................................................................................................................................................ 16

Block Protection Settings ............................................................................................................................ 17

Flag Status Register ......................................................................................................................................... 18

Extended Address Register .............................................................................................................................. 19

Internal Configuration Register ....................................................................................................................... 20

Nonvolatile Configuration Register .................................................................................................................. 21

Volatile Configuration Register ........................................................................................................................ 23

Supported Clock Frequencies ..................................................................................................................... 24

Enhanced Volatile Configuration Register ........................................................................................................ 27

Security Registers ........................................................................................................................................... 28

Sector Protection Security Register .................................................................................................................. 29

Nonvolatile and Volatile Sector Lock Bits Security ............................................................................................ 30

Volatile Lock Bit Security Register .................................................................................................................... 30

Device ID Data ............................................................................................................................................... 31

Serial Flash Discovery Parameter Data ............................................................................................................. 32

Command Definitions .................................................................................................................................... 33

Software RESET Operations ............................................................................................................................ 39

RESET ENABLE and RESET MEMORY Commands ....................................................................................... 39

READ ID Operations ....................................................................................................................................... 40

READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 40

READ SERIAL FLASH DISCOVERY PARAMETER Operation .............................................................................. 41

READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 41

READ MEMORY Operations ............................................................................................................................ 42

4-BYTE READ MEMORY Operations ................................................................................................................ 43

READ MEMORY Operations Timings ............................................................................................................... 44

WRITE ENABLE/DISABLE Operations ............................................................................................................. 51

READ REGISTER Operations ........................................................................................................................... 52

WRITE REGISTER Operations ......................................................................................................................... 54

CLEAR FLAG STATUS REGISTER Operation ..................................................................................................... 56

PROGRAM Operations .................................................................................................................................... 57

4-BYTE PROGRAM Operations ........................................................................................................................ 58

PROGRAM Operations Timings ....................................................................................................................... 58

ERASE Operations .......................................................................................................................................... 61

SUSPEND/RESUME Operations ..................................................................................................................... 63

PROGRAM/ERASE SUSPEND Operations .................................................................................................... 63

PROGRAM/ERASE RESUME Operations ...................................................................................................... 63

ONE-TIME PROGRAMMABLE Operations ....................................................................................................... 65

READ OTP ARRAY Command ...................................................................................................................... 65

PROGRAM OTP ARRAY Command .............................................................................................................. 65

ADDRESS MODE Operations .......................................................................................................................... 67

ENTER and EXIT 4-BYTE ADDRESS MODE Command ................................................................................ 67

DEEP POWER-DOWN Operations ................................................................................................................... 67

09005aef8661dcd4

mt25q-qlkt-L02-CBB-S-IT.pdf - Rev. F 10/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb, 3V Multiple I/O Serial Flash Memory

Features

ENTER DEEP POWER-DOWN Command ....................................................................................................

RELEASE FROM DEEP POWER-DOWN Command .......................................................................................

DEEP POWER-DOWN Timings ....................................................................................................................

QUAD PROTOCOL Operations ........................................................................................................................

ENTER or RESET QUAD INPUT/OUTPUT MODE Command .......................................................................

CYCLIC REDUNDANCY CHECK Operations ....................................................................................................

Cyclic Redundancy Check ...........................................................................................................................

State Table .....................................................................................................................................................

XIP Mode .......................................................................................................................................................

Activate and Terminate XIP Using Volatile Configuration Register .................................................................

Activate and Terminate XIP Using Nonvolatile Configuration Register ..........................................................

Confirmation Bit Settings Required to Activate or Terminate XIP ..................................................................

Terminating XIP After a Controller and Memory Reset .................................................................................

Power-Up and Power-Down ............................................................................................................................

Power-Up and Power-Down Requirements ..................................................................................................

Active, Standby, and Deep Power-Down Modes ................................................................................................

Power Loss and Interface Rescue .....................................................................................................................

Recovery ....................................................................................................................................................

Power Loss Recovery ...................................................................................................................................

Interface Rescue .........................................................................................................................................

Initial Delivery Status .....................................................................................................................................

Absolute Ratings and Operating Conditions .....................................................................................................

DC Characteristics and Operating Conditions ..................................................................................................

AC Characteristics and Operating Conditions ..................................................................................................

AC Reset Specifications ...................................................................................................................................

Program/Erase Specifications .........................................................................................................................

Revision History .............................................................................................................................................

Rev. F - 10/18 ..............................................................................................................................................

Rev. E - 01/18 ..............................................................................................................................................

Rev. D - 12/17 .............................................................................................................................................

Rev. C -10/16 ..............................................................................................................................................

Rev. B - 06/16 .............................................................................................................................................

Rev. A – 08/15 .............................................................................................................................................

09005aef8661dcd4

mt25q-qlkt-L02-CBB-S-IT.pdf - Rev. F 10/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

2Gb, 3V Multiple I/O Serial Flash Memory

Features

List of Figures

Figure 1: Part Number Ordering Information .................................................................................................... 2

Figure 2: Block Diagram .................................................................................................................................. 9

Figure 3: Logic Diagram ................................................................................................................................. 10

Figure 4: 24-Ball T-BGA, 5 x 5 (Balls Down) ..................................................................................................... 11

Figure 5: 24-Ball T-PBGA (5 x 5 ball grid array) – 6mm x 8mm .......................................................................... 13

Figure 6: Internal Configuration Register ........................................................................................................ 20

Figure 7: Sector and Password Protection ....................................................................................................... 28

Figure 8: RESET ENABLE and RESET MEMORY Command ............................................................................. 39

Figure 9: READ ID and MULTIPLE I/O READ ID Commands ........................................................................... 40

Figure 10: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah ................................................... 41

Figure 11: READ – 03h/13h

........................................................................................................................... 44

Figure 12: FAST READ – 0Bh/0Ch

................................................................................................................. 44

Figure 13: DUAL OUTPUT FAST READ – 3Bh/3Ch

......................................................................................... 45

Figure 14: DUAL INPUT/OUTPUT FAST READ – BBh/BCh

............................................................................ 45

Figure 15: QUAD OUTPUT FAST READ – 6Bh/6Ch

........................................................................................ 46

Figure 16: QUAD INPUT/OUTPUT FAST READ – EBh/ECh

............................................................................ 46

Figure 17: QUAD INPUT/OUTPUT WORD READ – E7h

................................................................................. 47

Figure 18: DTR FAST READ – 0Dh/0Eh

.......................................................................................................... 48

Figure 19: DTR DUAL OUTPUT FAST READ – 3Dh

........................................................................................ 48

Figure 20: DTR DUAL INPUT/OUTPUT FAST READ – BDh

............................................................................ 49

Figure 21: DTR QUAD OUTPUT FAST READ – 6Dh

........................................................................................ 50

Figure 22: DTR QUAD INPUT/OUTPUT FAST READ – EDh

............................................................................ 50

Figure 23: WRITE ENABLE and WRITE DISABLE Timing ................................................................................. 51

Figure 24: READ REGISTER Timing ................................................................................................................ 52

Figure 25: WRITE REGISTER Timing .............................................................................................................. 55

Figure 26: CLEAR FLAG STATUS REGISTER Timing ........................................................................................ 56

Figure 27: PAGE PROGRAM Command .......................................................................................................... 58

Figure 28: DUAL INPUT FAST PROGRAM Command ...................................................................................... 59

Figure 29: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 59

Figure 30: QUAD INPUT FAST PROGRAM Command ..................................................................................... 60

Figure 31: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 60

Figure 32: SUBSECTOR , SECTOR ERASE and DIE ERASE Timing .................................................................... 62

Figure 33: PROGRAM/ERASE SUSPEND and RESUME Timing ........................................................................ 64

Figure 34: READ OTP ARRAY Command Timing ............................................................................................. 65

Figure 35: PROGRAM OTP Command Timing ................................................................................................. 66

Figure 36: ENTER DEEP POWER-DOWN Timing ............................................................................................. 68

Figure 37: RELEASE FROM DEEP POWER-DOWN Timing ............................................................................... 69

Figure 38: XIP Mode Directly After Power-On .................................................................................................. 74

Figure 39: Power-Up Timing .......................................................................................................................... 77

Figure 40: AC Timing Input/Output Reference Levels ...................................................................................... 81

Figure 41: Reset AC Timing During PROGRAM and ERASE Cycle ..................................................................... 88

Figure 42: Reset Enable and Reset Memory Timing ......................................................................................... 88

Figure 43: Serial Input Timing STR ................................................................................................................. 88

Figure 44: Serial Input Timing DTR ................................................................................................................ 89

Figure 45: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 89

Figure 46: Hold Timing .................................................................................................................................. 89

Figure 47: Output Timing for STR ................................................................................................................... 90

Figure 48: Output Timing for DTR .................................................................................................................. 90

09005aef8661dcd4

mt25q-qlkt-L02-CBB-S-IT.pdf - Rev. F 10/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT25QL02GCBB8E12-0AAT TR Related Products

	MT25QL02GCBB8E12-0AAT TR	MT25QL02GCBB8E12-0SIT TR	MT25QL02GCBB8E12-0AAT
Description	NOR FlashSPI FLASH NOR SLC 512MX4 TBGA QDP	NOR Flash SERIAL NOR SLC 512MX4 TBGA QDP	NOR FlashSPI FLASH NOR SLC 512MX4 TBGA QDP
Maker	Micron	Micron	Micron
Product Category	NOR flash memory	NOR flash memory	NOR flash memory
Installation style	SMD/SMT	SMD/SMT	SMD/SMT
Package/box	T-PBGA-24	T-PBGA-24	T-PBGA-24
series	MT25QL	MT25QL	MT25QL
storage	2 Gbit	2 Gbit	2 Gbit
maximum clock frequency	166 MHz	166 MHz	166 MHz
Interface Type	SPI	SPI	SPI
organize	256 M x 8	256 M x 8	256 M x 8
Timing type	Synchronous	Synchronous	Synchronous
Data bus width	8 bit	8 bit	8 bit
Supply voltage - min.	2.7 V	2.7 V	2.7 V
Supply voltage - max.	3.6 V	3.6 V	3.6 V
Supply current—max.	110 mA	94 mA	110 mA
Minimum operating temperature	- 40 C	- 40 C	- 40 C
Maximum operating temperature	+ 105 C	+ 85 C	+ 105 C
Encapsulation	Reel	Reel	Tray
speed	166 MHz	166 MHz	166 MHz
Factory packaging quantity	2000	2500	1122
storage type	NOR	NOR	-
standard	Not Supported	Not Supported	-

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