Operating Temperature Range ..........................
-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................
-55°C to +125°C
Lead Temperature (soldering, 10s)
.................................
+300°C
Soldering Temperature (reflow) ......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
1-Wire Pullup Resistance
Input Capacitance
Input Load Current
High-to-Low Switching Threshold
Input Low Voltage
Low-to-High Switching Threshold
Switching Hysteresis
Output Low Voltage
Recovery Time
Time Slot Duration
Reset Low Time
Reset High Time
Presence Detect Sample Time
IO PIN: 1-Wire WRITE
Write-Zero Low Time
Write-One Low Time
IO PIN: 1-Wire READ
Read Low Time
Read Sample Time
t
RL
t
MSR
(Notes 2, 17)
(Notes 2, 17)
0.25
t
RL
+ δ
2 - δ
2
µs
µs
t
W0L
t
W1L
(Notes 2, 16)
(Notes 2, 16)
8
0.25
16
2
µs
µs
V
PUP
R
PUP
C
IO
I
L
V
TL
V
IL
V
TH
V
HY
V
OL
t
REC
t
SLOT
t
RSTL
t
RSTH
t
MSP
(Note 2)
V
PUP
= 2.75V to 3.63V (Note 3)
V
PUP
= 1.71V to 2.75V (Note 3)
(Notes 4, 5)
IO pin at V
PUP
IO pin at V
PUP
= 1.8V+5%
(Notes 6, 7)
V
PUP
= 2.75V to 3.63V (Notes 2, 8)
V
PUP
= 1.71V to 2.75V (Notes 2, 8)
(Notes 6, 9)
V
PUP
= 2.75V to 3.63V (Notes 6, 10)
V
PUP
= 1.71V to 2.75V (Notes 6, 10)
V
PUP
= 1.89V to 3.63V, I
OL
= 4mA (Note 11)
V
PUP
= 1.71V to 1.89V, I
OL
= 2mA (Note 11)
(Notes 2, 12)
(Notes 2, 13)
(Note 2)
(Note 14)
(Notes 2, 15)
5
13
48
48
8
10
80
0.75 x
V
PUP
0.3
0.17
0.4
0.4
µs
µs
µs
µs
µs
V
1.71
300
300
1500
5
2
0.65 x
V
PUP
0.5
0.3
V
V
20
8
3.63
1500
750
V
Ω
pF
µA
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
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Maxim Integrated
│
2
DS28E05
1-Wire EEPROM
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
EEPROM
Programming Current
Programming Time for a 16-Bit
Segment
Write/Erase Cycling Endurance
Data Retention
I
PROG
t
PROG
N
CY
t
DR
(Notes 5, 18)
(Note 19)
T
A
= +85°C (Notes 20, 21)
T
A
= +85°C (Notes 22, 23, 24)
1000
10
400
16
µA
ms
—
Years
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:
System requirement.
Note 3:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4:
Typical value represents the internal parasite capacitance when V
PUP
is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5:
Guaranteed by design and/or characterization only. Not production tested.
Note 6:
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage, which is a function of V
PUP
, R
PUP
, 1-Wire timing, and
capacitive loading on IO. Lower V
PUP
, higher R
PUP
, shorter t
REC
, and heavier capacitive loading all lead to lower values of
V
TL
, V
TH
, and V
HY
.
Note 7:
Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8:
The voltage on IO must be less than or equal to V
ILMAX
at all times the master is driving IO to a logic 0 level.
Note 9:
Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10: After V
TH
is crossed during a rising edge on IO, the voltage on IO must drop by at least V
HY
to be detected as logic 0.
Note 11: The I-V characteristic is linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: Defines maximum possible bit rate. Equal to 1/(t
W0LMIN
+ t
RECMIN
).
Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15:
Interval after t
RSTL
during which a bus master can read a logic 0 on IO if there is a DS28E05 present. The power-up pres-
ence detect pulse could be outside this interval but will be complete within 2ms for a 3.3V V
PUP
or 20ms for a 1.8V V
PUP
after power-up.
Note 16: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
. The actual
maximum duration for the master to pull the line low is t
W1LMAX
+ t
F
- ε and t
W0LMAX
+ t
F
- ε, respectively.
Note 17: δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is t
RLMAX
+ t
F
.
Note 18: Current drawn from IO during the EEPROM programming interval, during which the voltage at IO must not drop below
1.69V.
Note 19:
The t
PROG
interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a
valid Write Memory sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I
PROG
to I
L
.
Note 20: Write-cycle endurance is tested in compliance with JESD47G.
Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22: Data retention is tested in compliance with JESD47G.
Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 24:
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.
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Maxim Integrated
│ 3
DS28E05
1-Wire EEPROM
Pin Configurations
TOP VIEW
1
IO 1
BOTTOM VIEW
2
+
+
DS28E05
+
A
3
GND
GND
IO
GND
IO
N.C.
1
2
3
DS28E05
6 N.C.
5 N.C.
4 N.C.
DS28E05GB+
DS28E05
B
GND
IO
GND
IO
0Drr
N.C. 2
SOT23
TSOC
UCSP
NOTE:
THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL
CONTACT USE CASES ONLY. NOT FOR SOLDERING.
SFN
(3.5mm x 5mm x 0.35mm)
Pin Descriptions
PIN
SFN
—
1
2
BUMP
—
A2, B2
A1, B1
SOT23
2
1
3
TSOC
3–6
2
1
NAME
N.C.
IO
GND
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Ground Reference
FUNCTION
Detailed Description
Overview
The DS28E05 combines 896 bits of user EEPROM orga-
nized as seven 128-bit pages, 64 bits of administrative
data memory, and a 64-bit ROM ID in a single chip. Data
is transferred serially through the 1-Wire protocol, which
requires only a single data lead and a ground return.
The user memory can have unrestricted write access (fac-
tory default), or can be write protected or put in EPROM
emulation mode. Write protection prevents changes to
the memory data. EPROM emulation mode logically
ANDs memory data with incoming new data, which allows
changing bits from 1 to 0, but not vice versa. By chang-
ing one bit at a time this mode could be used to create
nonvolatile nonresettable counters. For more details
refer to
Application Note 5042: Implementing
Nonvolatile,
Nonresettable Counters for Embedded Systems.
The device’s 64-bit ROM ID can be used to electronically
identify the equipment in which the DS28E05 is used.
The ROM ID guarantees unique identification and is also
used to address the device in a multidrop 1-Wire network
environment, where multiple devices reside on a com-
mon 1-Wire bus and operate independently of each other.
Applications include accessory/PCB identification, medi-
cal sensor calibration data storage, analog sensor calibra-
tion, and after-market management of consumables.
The block diagram in
Figure 1
shows the relationships
between the major control and memory sections of the
DS28E05. The DS28E05 has three main data compo-
nents: seven 128-bit pages of user EEPROM, 64 bits
of administrative data memory, and a 64-bit ROM ID.
Figure 2
shows the hierarchic structure of the 1-Wire
protocol. The bus master must first provide one of the
five ROM function commands: Read ROM, Match ROM,
Search ROM, Skip ROM, or Resume Communication.
The protocol required for these ROM function commands
is described in
Figure 8. After a ROM function command
is successfully executed, the memory functions become
accessible and the master can select one of the two
memory function commands. The function protocols are
described in
Figure 6.
All data is read and written least
significant bit first.
64-Bit ROM ID
Each DS28E05 contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a
cyclic redundancy check (CRC) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using
a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4.
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Maxim Integrated
│
4
DS28E05
1-Wire EEPROM
PARASITE POWER
1-Wire NET
1-Wire FUNCTION
CONTROL
64-BIT
ROM ID
DS28E05
MEMORY
FUNCTION
CONTROL
USER EEPROM
7 PAGES OF
(128 BITS EACH)
ADMINISTRATIVE DATA
(64 BITS)
Figure 1. Block Diagram
DS28E05
COMMAND LEVEL:
AVAILABLE COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
DATA FIELD AFFECTED:
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
1-Wire ROM
FUNCTION COMMANDS
DS28EL05-SPECIFIC
MEMORY FUNCTION COMMANDS
WRITE MEMORY
READ MEMORY
USER MEMORY, ADMINISTRATIVE DATA
USER MEMORY, ADMINISTRATIVE DATA
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSb
8-BIT
CRC CODE
MSb
LSb MSb
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE
(0Dh)
LSb MSb
LSb
LSb
Figure 3. 64-Bit ROM ID
The polynomial is X
8
+ X
5
+ X
4
+ 1. Additional information
about the 1-Wire Cyclic Redundancy Check is available
in
Application Note 27: Understanding
and Using Cyclic
Redundancy Checks with Maxim iButton® Products.
iButton is a registered trademark of Maxim Integrated
Products, Inc.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift reg-
ister contains the CRC value. Shifting in the 8 bits of the
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