W9812G2KB
1M
4 BANKS
32 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
ORDER INFORMATION ............................................................................................................. 4
BALL CONFIGURATION ............................................................................................................ 5
BALL DESCRIPTION .................................................................................................................. 6
BLOCK DIAGRAM (SINGLE CHIP) ............................................................................................ 7
FUNCTIONAL DESCRIPTION.................................................................................................... 8
7.1
Power Up and Initialization ............................................................................................. 8
7.2
Programming Mode Register Set command .................................................................. 8
7.3
Bank Activate Command ................................................................................................ 8
7.4
Read and Write Access Modes ...................................................................................... 8
7.5
Burst Read Command .................................................................................................... 9
7.6
Burst Command .............................................................................................................. 9
7.7
Read Interrupted by a Read ........................................................................................... 9
7.8
Read Interrupted by a Write ............................................................................................ 9
7.9
Write Interrupted by a Write ............................................................................................ 9
7.10 Write Interrupted by a Read ............................................................................................ 9
7.11 Burst Stop Command ................................................................................................... 10
7.12 Addressing Sequence of Sequential Mode .................................................................. 10
7.13 Addressing Sequence of Interleave Mode .................................................................... 10
7.14 Auto-precharge Command ........................................................................................... 11
7.15 Precharge Command .................................................................................................... 11
7.16 Self Refresh Command ................................................................................................ 11
7.17 Power Down Mode ....................................................................................................... 12
7.18 No Operation Command ............................................................................................... 12
7.19 Deselect Command ...................................................................................................... 12
7.20 Clock Suspend Mode .................................................................................................... 12
OPERATION MODE ................................................................................................................. 13
ELECTRICAL CHARACTERISTICS ......................................................................................... 14
9.1
Absolute Maximum Ratings .......................................................................................... 14
9.2
Recommended DC Operating Conditions .................................................................... 14
9.3
Capacitance .................................................................................................................. 14
9.4
DC Characteristics ........................................................................................................ 15
9.5
AC Characteristics and Operating Condition ................................................................ 16
TIMING WAVEFORMS ............................................................................................................. 18
10.1 Command Input Timing ................................................................................................ 18
10.2 Read Timing.................................................................................................................. 19
10.3 Control Timing of Input/Output Data ............................................................................. 20
Publication Release Date: Feb. 23, 2017
Revision: A01
8.
9.
10.
-1-
W9812G2KB
10.4 Mode Register Set Cycle .............................................................................................. 21
OPERATINOPERATING TIMING EXAMPLE ........................................................................... 22
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ...................................... 22
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ........... 23
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ...................................... 24
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ........... 25
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 26
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28
11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 30
11.10 Auto-precharge Write (Burst Length = 4) .................................................................... 31
11.11 Auto Refresh Cycle ..................................................................................................... 32
11.12 Self Refresh Cycle ....................................................................................................... 33
11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) ............................. 34
11.14 Power down Mode ....................................................................................................... 35
11.15 Auto-precharge Timing (Write Cycle) .......................................................................... 36
11.16 Auto-precharge Timing (Read Cycle) .......................................................................... 37
11.17 Timing Chart of Read to Write Cycle ........................................................................... 38
11.18 Timing Chart of Write to Read Cycle ........................................................................... 38
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .......................................... 39
11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
11.21 CKE/DQM Input Timing (Write Cycle) ......................................................................... 40
11.22 CKE/DQM Input Timing (Read Cycle) ......................................................................... 41
PACKAGE SPECIFICATION .................................................................................................... 42
REVISION HISTORY ................................................................................................................ 43
11.
12.
13.
-2-
Publication Release Date: Feb. 23, 2017
Revision: A01
W9812G2KB
1. GENERAL DESCRIPTION
W9812G2KB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words
4 banks
32 bits. W9812G2KB delivers a data bandwidth of up to 166M words per
second. To fully comply with the personal computer industrial standard, W9812G2KB is sorted into
two grade parts: -6 and -6I. The -6 and-6I grade parts are compliant to the 166MHz/CL3 specification
(the -6I industrial grade which is guaranteed to support -40°C ≤ T
A
≤ 85°C).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.By
having a programmable Mode Register, the system can change burst length, latency cycle, interleave
or sequential burst to maximize its performance. W9812G2KB is ideal for main memory in high
performance applications.
2. FEATURES
3.3V ± 0.3V power supply
1,048,576 words 4 banks
32 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by DQM0-3
Auto-precharge and controlled precharge
Burst read, single write operation
4K refresh cycles/64mS
Interface: LVTTL
Packaged in TFBGA 90 Ball (8 x13 mm
2
), using Lead free materials with RoHS compliant
Dual-Die-Package (DDP), two pieces of 64M bits chip sealed in one package
-3-
Publication Release Date: Feb. 23, 2017
Revision: A01
W9812G2KB
BLOCK DIAGRAM (DDP)
CLK
CLK
VDD
VDD
CKE
CKE
VDDQ
VDDQ
CS
CS
VSS
VSS
CAS, RAS, WE
CAS, RAS, WE
64M (x16) bits
SDRAM 1
VSSQ
VSSQ
BS0, BS1
BS0, BS1
LDQM, UDQM
DQM0, DMQ1
A[11:0]
A[11:0]
DQ[15:0]
DQ[15:0]
CLK
VDD
CKE
VDDQ
CS
VSS
CAS, RAS, WE
64M (x16) bits
SDRAM 2
VSSQ
BS0, BS1
LDQM, UDQM
DQM2, DQM3
A[11:0]
DQ[15:0]
DQ[31:16]
Note:
There two same 4M x16 SDRAM chips sealed in this product. The specification in the following
pages are for the one chip, the 64M bits SDRAM’ except output slew rate, I
DD
and ball capacitance.
Although each die is tested individually within the dual-die package, some stacked die test results
may vary from a like-die tested within a monolithic die package.
3. ORDER INFORMATION
PART NUMBER
SPEED
SELF REFRESH
CURRENT (MAX.)
OPERATING
TEMPERATURE
W9812G2KB-6
W9812G2KB-6I
166MHz/CL3
166MHz/CL3
4mA
4mA
0°C ~ 70°C
-40°C ~ 85°C
-4-
Publication Release Date: Feb. 23, 2017
Revision: A01
W9812G2KB
4. BALL CONFIGURATION
Top View
1
A
DQ26
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BS0
CAS#
VDD
DQ6
DQ1
VDDQ
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BS1
CS#
WE#
DQ7
DQ5
DQ3
VSSQ
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
2
3
4
5
6
7
8
9
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1
L
VDDQ
M
VSSQ
N
VSSQ
P
DQ11
R
DQ13
VDD
DQ0
DQ2
-5-
Publication Release Date: Feb. 23, 2017
Revision: A01
京公网安备 11010802033920号
EEWORLD
