MT41K128M8DA-107 AIT:J TR datasheet, PDF

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MT41K128M8DA-107 AIT:J TR: DescriptionDynamic Random Access Memory DDR3 1G 128MX8 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size418KB，21 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT41K128M8DA-107 AIT:J TR Overview

Dynamic Random Access Memory DDR3 1G 128MX8 FBGA

MT41K128M8DA-107 AIT:J TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM - DDR3L
Data bus width	8 bit
organize	128 M x 8
Package/box	FBGA-78
storage	1 Gbit
maximum clock frequency	933 MHz
Supply voltage - max.	1.45 V
Supply voltage - min.	1.283 V
Supply current—max.	162 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 95 C
series	MT41K
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	2000

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1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Description

Addendum Automotive DDR3L SDRAM

MT41K128M8 – 16 Meg x 8 x 8 banks

MT41K64M16 – 8 Meg x 16 x 8 banks

Description

This addendum provides information to add Automo-

tive Ultra-high Temperature (AUT) option for the data

sheet. This addendum does not provide detailed infor-

mation about the device. Refer to the data sheet (1Gb:

x8, x16 Automotive DDR3L SDRAM, Rev. B 2/15 EN)

for a complete description of device functionality, op-

erating modes, and specifications for the same Micron

part number products. The 1.35V DDR3L SDRAM de-

vice is a low-voltage version of the 1.5V DDR3 SDRAM

device. Refer to the DDR3 (1.5V) SDRAM data sheet

specifications when running in 1.5V compatible

mode.

•

Write leveling

Multipurpose register

Output driver calibration

AEC-Q100

PPAP submission

8D response time

Options

• Configuration

– 128 Meg x 8

– 64 Meg x 16

• FBGA package (Pb-free) – x8

– 78-ball FBGA (8mm x 10.5mm)

• FBGA package (Pb-free) – x16

– 96-ball FBGA (8mm x 14mm)

• Timing – cycle time

– 1.07ns @ CL = 13 (DDR3-1866)

• Product certification

– Automotive

• Operating temperature

– Industrial (–40°C

≤

+95°C)

– Automotive (–40°C

≤

+105°C)

– Ultra-high (–40°C

≤

+125°C)

• Revision

Notes:

Marking

128M8

64M16

-107

Features

•

= V

DDQ

= 1.35V (1.283V to 1.45V)

Backward compatible to V

= V

DDQ

= 1.5V ±0.075V

Differential bidirectional data strobe

8n-bit prefetch architecture

Differential clock inputs (CK, CK#)

8 internal banks

Nominal and dynamic on-die termination (ODT)

for data, strobe, and mask signals

Programmable CAS (READ) latency (CL)

Programmable CAS additive latency (AL)

Programmable CAS (WRITE) latency (CWL)

Fixed burst length (BL) of 8 and burst chop (BC) of 4

(via the mode register set [MRS])

Selectable BC4 or BL8 on-the-fly (OTF)

Self refresh mode

of –40°C to 125°C

– 64ms, 8192-cycle refresh at –40°C to 85°C

– 32ms at 85°C to 105°C

– 16ms at 105°C to 115°C

– 8ms at 115°C to 125°C

Self refresh temperature (SRT)

Automatic self refresh (ASR)

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on http://www.micron.com

for available offerings.

2. The datasheet does not support ×4 mode

even though ×4 mode description exists in

the following sections.

3. The UT option use based on automotive us-

age model. Contact Micron sales represen-

tative for further information.

•

Table 1: Key Timing Parameters

Speed Grade

-107

Data Rate (MT/s)

1866

Target

RCD-

RP-CL

13-13-13

RCD

(ns)

CL (ns)

13.91

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. D 5/18 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,

including without limitation specifications and product descriptions. This document supersedes and replaces all

information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-

ment if you obtain the product described herein from any unauthorized distributor or other source not authorized

by Micron.

Automotive Applications.

Products are not designed or intended for use in automotive applications unless specifi-

cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-

utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-

automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-

ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron

products are not designed or intended for use in automotive applications unless specifically designated by Micron

as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-

demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'

fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage

resulting from any use of non-automotive-grade products in automotive applications.

Critical Applications.

Products are not authorized for use in applications in which failure of the Micron compo-

nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage

("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-

mental damage by incorporating safety design measures into customer's applications to ensure that failure of the

Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron

component for any critical application, customer and distributor shall indemnify and hold harmless Micron and

its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,

costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of

product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-

cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the

Micron product.

Customer Responsibility.

Customers are responsible for the design, manufacture, and operation of their systems,

applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-

URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE

WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR

PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included

in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-

vironmental damages will result from failure of any semiconductor component.

Limited Warranty.

In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential

damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,

breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly

authorized representative.

Functional Description

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.

The double data rate architecture is an 8n-prefetch architecture with an interface de-

signed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. D 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb: x8, x16 Automotive DDR3L SDRAM Addendum

Functional Description

cycle data transfer at the internal DRAM core and eight corresponding

n-bit-wide,

one-

half-clock-cycle data transfers at the I/O pins.

The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for

use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data

for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the

data strobes.

The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK

going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com-

mand, and address signals are registered at every positive edge of CK. Input data is reg-

istered on the first rising edge of DQS after the WRITE preamble, and output data is ref-

erenced on the first rising edge of DQS after the READ preamble.

Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se-

lected location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVATE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with

the ACTIVATE command are used to select the bank and row to be accessed. The ad-

dress bits registered coincident with the READ or WRITE commands are used to select

the bank and the starting column location for the burst access.

The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

access.

As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM

allows for concurrent operation, thereby providing high bandwidth by hiding row pre-

charge and activation time.

A self refresh mode is provided, along with a power-saving, power-down mode.

Industrial Temperature

The industrial temperature (IT) device requires that the case temperature not exceed

–40°C or 95°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when T

is <0°C or

>85°C.

Automotive Temperature

The automotive temperature (AT) device requires that the case temperature not exceed

–40°C or 105°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature self refresh option. Additionally,

ODT resistance and the input/output impedance must be derated when T

is <0°C or

>85°C.

Utra-high Temperature

The Utra-high temperature (UT) device requires that the case temperature not exceed

–40°C or 125°C. JEDEC specifications require the refresh rate to double when T

exceeds

85°C; this also requires use of the high-temperature auto refresh option. When T

+85°C, the refresh rate must be increased to 2X, when T

> +105°C, the refresh rate must

be increased to 4X and when T

> +115°C, the refresh rate must be increased to 8X. Self-

09005aef86775d6d

1gb_aut_DDR3L_1_35v_addendum.pdf - Rev. D 5/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT41K128M8DA-107 AIT:J TR Related Products

	MT41K128M8DA-107 AIT:J TR	MT41K64M16TW-107 AIT:J TR	MT41K64M16TW-107 AAT:J TR	MT41K64M16TW-107 AUT:J TR	MT41K64M16TW-107 AIT:J	MT41K128M8DA-107 AIT:J	MT41K64M16TW-107 AAT:J	MT41K64M16TW-107 AUT:J
Description	Dynamic Random Access Memory DDR3 1G 128MX8 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA	Dynamic Random Access Memory DDR3 1G 128MX8 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA	Dynamic Random Access Memory DDR3 1G 64MX16 FBGA
Maker	Micron	Micron	Micron	Micron	Micron	Micron	Micron	Micron
Product Category	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory
Package/box	FBGA-78	FBGA-96	FBGA-96	FBGA-96	FBGA-96	FBGA-78	FBGA-96	FBGA-96
series	MT41K	MT41K	MT41K	MT41K	MT41K	MT41K	MT41K	MT41K
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Factory packaging quantity	2000	2000	2000	2000	1368	1440	1368	1368
Encapsulation	Reel	Reel	Reel	Reel	Tray	Tray	Tray	Tray

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