Acronyms in This Document .................................................................................................................................................5
3. Features ........................................................................................................................................................................9
FIR Filter Architecture .......................................................................................................................................10
4.2.3. Polyphase Interpolation FIR Filter .................................................................................................................11
4.2.4. Polyphase Decimation FIR Filter ...................................................................................................................12
4.2.5. Multi-channel FIR Filters ...............................................................................................................................12
Configuring the FIR Filter Core ..........................................................................................................................14
Memory Type .......................................................................................................................................15
4.5.
Signal Descriptions ............................................................................................................................................16
4.6.
Interfacing with the FIR Filter IP Core ...............................................................................................................17
4.6.1. Data interface ...............................................................................................................................................17
6. IP Core Generation and Evaluation.............................................................................................................................27
6.1.
Licensing the IP Core .........................................................................................................................................27
6.2.
Getting Started ..................................................................................................................................................27
6.3.
IPexpress-Created Files and Top Level Directory Structure ..............................................................................31
6.4.
Instantiating the Core........................................................................................................................................32
6.7.1. Enabling Hardware Evaluation in Diamond...................................................................................................33
6.8.
Updating/Regenerating the IP Core ...................................................................................................................33
6.8.1. Regenerating an IP Core in Diamond ............................................................................................................33
6.9.
Regenerating an IP Core in Clarity Designer Tool ..............................................................................................34
6.10. Recreating an IP Core in Clarity Designer Tool ..................................................................................................34
Technical Support Assistance .............................................................................................................................................36
Appendix A. Resource Utilization .......................................................................................................................................37
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Revision History .................................................................................................................................................................. 38
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-IPUG-02043-1.5
3
FIR Filter IP Core
User Guide
Figures
Figure 4.1. Top-Level Interface for the FIR Filter IP Core ....................................................................................................10
Figure 4.2. Direct-form FIR Filter ........................................................................................................................................11
Figure 4.3. Symmetric Coefficients FIR Filter Implementation ...........................................................................................11
Figure 4.7. Tap and Coefficient Memory Management for a Sample FIR Filter .................................................................13
Figure 4.8. Single Channel, Single Rate FIR Filter with Continuous Inputs .........................................................................18
Figure 4.9. Single Channel, Single Rate FIR Filter with Gaps in Input .................................................................................18
Figure 4.12. Multi-Channel Single Rate FIR Filter (3 Channels) ..........................................................................................19
Figure 4.13. Multi-Channel (3 Channels) Interpolator (Factor of 3) ...................................................................................19
Figure 4.14. Multi-Channel (3 Channels) Decimator (Factor of 3) ......................................................................................19
Figure 4.15. Multi-Channel Single Rate FIR Filter (3 Channels) ..........................................................................................20
Figure 4.16. Multi-Channel (3 Channels) Interpolator (Factor of 3) ...................................................................................20
Figure 4.17. Multi-Channel (3 Channels) Decimator (Factor of 3) ......................................................................................20
Figure 5.1. Architecture Tab of the FIR Filter IP Core Interface ..........................................................................................22
Figure 5.2. I/O Specification Tab of the FIR Filter IP Core Interface ...................................................................................24
Figure 5.3. Implementation Tab of the FIR Filter IP Core Interface ....................................................................................26
Figure 6.5. Fir Filter Dialog Box ...........................................................................................................................................29
Figure 6.6. IP Configuration Interface .................................................................................................................................30
Figure 6.7. FIR Filter IP Core Generated Directory Structure..............................................................................................31
Tables
Table 2.1. FIR Filter IP Core for LatticeXP2 Devices Quick Facts ...........................................................................................7
Table 2.2. FIR Filter IP Core for LatticeECP3 Devices Quick Facts .........................................................................................7
Table 2.3. FIR Filter IP Core for LatticeECP5 Devices Quick Facts .........................................................................................8
Table 4.1. Maximum Multiplier Multiplexing Factor for Different Configurations* ...........................................................15
Table 4.2. Top-Level Port Definitions ..................................................................................................................................16
Table 5.1. Parameter Specifications for the FIR Filter IP Core ............................................................................................21
Table 6.1. File List ...............................................................................................................................................................31
Table A.1. Performance and Resource Utilization (LatticeECP3)* ......................................................................................37
Table A.2. Performance and Resource Utilization (LatticeXP2)* ........................................................................................37
Table A.3. Performance and Resource Utilization (LFE5U)* ...............................................................................................37
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
1 System Overview The programmable current source has the characteristics of wide output current range, high accuracy and high power. It is an essential instrument for automatic test system and calibr...
The ISO 10536 standard was mainly developed between 1992 and 1995. Due to the high cost of this card and few advantages over contact IC cards, this card has never been sold on the market. The ISO 1444...
[i=s] This post was last edited by dontium on 2015-1-23 11:23 [/i] When using op amps for signal amplification, people only pay attention to the results and never consider the noise problem. The book ...
Hello everyone! I see that both LM3S8962 and 9B96 in TI routines use ASSERT, which is the function for judging errors. I also know that I need to include the debug.h file, but how can I see the effect...
[url=https://www.eeworld.com.cn]www.eeworld.com.cn[/url] I found some information about TI Stellaris during the learning process, and would like to share it with you!...
In recent years, lighting has become an important area that countries around the world are targeting to promote energy conservation and environmental protection. According to statistics, about 20% ...[Details]
Editor's note: In order to help technicians or engineers who have knowledge of PIC microcontroller assembly language quickly master the method of using C language to program PIC microcontrollers, t...[Details]
Instrument stepper motor
The stepper motor is an open-loop control element that converts electrical pulse signals into angular displacement or linear displacement. In the case of non...[Details]
1. Background:
The instrument system parameter detection and control of the chemical production workshop of Tangshan Coal Gas Coking Plant are all analog instruments, some of which are eve...[Details]
1 Introduction
Building Automation System (BAS) is a distributed monitoring system (DCS) designed according to distributed information and control theory. It is the result of the mutual de...[Details]
1 Introduction
With the development of control, computer, communication, network technology, etc., a new control technology, namely fieldbus, has emerged in the field of industrial control...[Details]
Abstract: The output of high-range acceleration sensor is less than 10 mV under the excitation of small signal. The noise of traditional test system may cover such small voltage signal, so that hig...[Details]
The DisplayPort interface standard is approved by the Video Electronics Standards Association (VESA) to provide an open, scalable standard for the entire industry. The development of DisplayPort ca...[Details]
1 Development of LED Film and Television Lighting
1.1 The significance of developing film and television lighting
Lighting power consumption accounts for a large proportion of the total p...[Details]
The emergence and development of street lamps are inseparable from the prosperity and progress of cities, which makes street lamps useful. Conversely, street lamps also make the night of the city n...[Details]
introduction
When it comes to the production of mobile phone lithium-ion batteries, the first thing that comes to mind is Japan's industrialized mechanical assembly line, NOKIO, MOTOLROLA's st...[Details]
Mobile phones, MP3s, tablet computers, laptops, digital cameras, handheld game consoles, navigation devices, etc., all these mobile devices are powered by mobile batteries, and the battery life is ...[Details]
introduction
The core features of mobile value-added service products are mobility, immediacy and personalization. Mobile value-added services are a new service mode that is rapidly developing...[Details]
Dual Tone MultiFrequency (DTMF) signaling is gradually being used in push-button telephones around the world. It quickly replaced the dial pulse signaling used in traditional rotary phones because ...[Details]
1 Introduction
Fieldbus is a serial, digital, multi-point communication data bus between field equipment/instruments installed in the production process area and automatic control devices/syst...[Details]
Power technology
京公网安备 11010802033920号
EEWORLD
