MT40A256M16GE-083E IT:B TR datasheet, PDF

Datasheet> All Categories > semiconductor> Memory IC> Dynamic random access memory> MT40A256M16GE-083E IT:B TR

MT40A256M16GE-083E IT:B TR: DescriptionDynamic Random Access Memory DDR4 4G 256MX16 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size12MB，384 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

Download Datasheet Parametric View All

MT40A256M16GE-083E IT:B TR Overview

Dynamic Random Access Memory DDR4 4G 256MX16 FBGA

MT40A256M16GE-083E IT:B TR Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM - DDR4
Data bus width	16 bit
organize	256 M x 16
Package/box	FBGA-96
storage	4 Gbit
maximum clock frequency	1200 MHz
Supply voltage - max.	1.26 V
Supply voltage - min.	1.14 V
Supply current—max.	83 mA
Minimum operating temperature	- 40 C
Maximum operating temperature	+ 95 C
series	MT40A
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	2000

Preview

Download Datasheet

View All

4Gb: x4, x8, x16 DDR4 SDRAM

Features

DDR4 SDRAM

MT40A1G4

MT40A512M8

MT40A256M16

Features

•

= V

DDQ

= 1.2V ±60mV

= 2.5V, –125mV/+250mV

On-die, internal, adjustable V

REFDQ

generation

1.2V pseudo open-drain I/O

maximum up to 95°C

– 64ms, 8192-cycle refresh up to 85°C

– 32ms, 8192-cycle refresh at >85°C to 95°C

16 internal banks (x4, x8): 4 groups of 4 banks each

8 internal banks (x16): 2 groups of 4 banks each

8n-bit prefetch architecture

Programmable data strobe preambles

Data strobe preamble training

Command/Address latency (CAL)

Multipurpose register READ and WRITE capability

Write leveling

Self refresh mode

Low-power auto self refresh (LPASR)

Temperature controlled refresh (TCR)

Fine granularity refresh

Self refresh abort

Maximum power saving

Output driver calibration

Nominal, park, and dynamic on-die termination

(ODT)

Data bus inversion (DBI) for data bus

Command/Address (CA) parity

Databus write cyclic redundancy check (CRC)

Per-DRAM addressability

Connectivity test

sPPR and hPPR capability

JEDEC JESD-79-4 compliant

Options

• Configuration

– 1 Gig x 4

– 512 Meg x 8

– 256 Meg x 16

• FBGA package (Pb-free) – x4, x8

– 78-ball (9mm x 11.5mm) – Rev. A

– 78-ball (9mm x 10.5mm) – Rev. B

– 78-ball (8mm x 12mm) – Rev. E

– 78-ball (7.5mm x 11mm) – Rev. F

• FBGA package (Pb-free) – x16

– 96-ball (9mm x 14mm) – Rev. A

– 96-ball (9mm x 14mm) – Rev. B

– 96-ball (7.5mm x 13.5mm) – Rev. E, F

• Timing – cycle time

– 0.625ns @ CL = 22 (DDR4-3200)

– 0.682ns @ CL = 20 (DDR4-2933)

– 0.682ns @ CL = 21 (DDR4-2933)

– 0.750ns @ CL = 18 (DDR4-2666)

– 0.750ns @ CL = 19 (DDR4-2666)

– 0.833ns @ CL = 16 (DDR4-2400)

– 0.833ns @ CL = 17 (DDR4-2400)

– 0.937ns @ CL = 15 (DDR4-2133)

– 0.937ns @ CL = 16 (DDR4-2133)

– 1.071ns @ CL = 13 (DDR4-1866)

• Operating temperature

– Commercial (0° T

95°C)

– Industrial (–40° T

95°C)

– Revision

Marking

1G4

512M8

256M16

-062E

-068E

-068

-075E

-075

-083E

-083

-093E

-093

-107E

None

•

Notes:

1. Not all options listed can be combined to

define an offered product. Use the part

catalog search on

http://www.micron.com

for available offerings.

2. Not available on Rev. A.

3. Restricted and limited availability.

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

4Gb: x4, x8, x16 DDR4 SDRAM

Features

Contents

Important Notes and Warnings .......................................................................................................................

General Notes and Description .......................................................................................................................

Description ................................................................................................................................................

Industrial Temperature ...............................................................................................................................

General Notes ............................................................................................................................................

Definitions of the Device-Pin Signal Level ...................................................................................................

Definitions of the Bus Signal Level ...............................................................................................................

Functional Block Diagrams .............................................................................................................................

Ball Assignments ............................................................................................................................................

Ball Descriptions ............................................................................................................................................

Package Dimensions .......................................................................................................................................

State Diagram ................................................................................................................................................

Functional Description ...................................................................................................................................

RESET and Initialization Procedure .................................................................................................................

Power-Up and Initialization Sequence .........................................................................................................

RESET Initialization with Stable Power Sequence .........................................................................................

Uncontrolled Power-Down Sequence ..........................................................................................................

Programming Mode Registers .........................................................................................................................

Mode Register 0 ..............................................................................................................................................

Burst Length, Type, and Order .....................................................................................................................

CAS Latency ...............................................................................................................................................

Test Mode ..................................................................................................................................................

Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................

DLL RESET .................................................................................................................................................

Mode Register 1 ..............................................................................................................................................

DLL Enable/DLL Disable ............................................................................................................................

Output Driver Impedance Control ...............................................................................................................

ODT R

TT(NOM)

Values ..................................................................................................................................

Additive Latency .........................................................................................................................................

DQ RX EQ ..................................................................................................................................................

Write Leveling ............................................................................................................................................

Output Disable ...........................................................................................................................................

Termination Data Strobe .............................................................................................................................

Mode Register 2 ..............................................................................................................................................

CAS WRITE Latency ....................................................................................................................................

Low-Power Auto Self Refresh .......................................................................................................................

Dynamic ODT ............................................................................................................................................

Write Cyclic Redundancy Check Data Bus ....................................................................................................

Mode Register 3 ..............................................................................................................................................

Multipurpose Register ................................................................................................................................

WRITE Command Latency When CRC/DM is Enabled .................................................................................

Fine Granularity Refresh Mode ....................................................................................................................

Temperature Sensor Status .........................................................................................................................

Per-DRAM Addressability ...........................................................................................................................

Gear-Down Mode .......................................................................................................................................

Mode Register 4 ..............................................................................................................................................

Hard Post Package Repair Mode ..................................................................................................................

Soft Post Package Repair Mode ....................................................................................................................

WRITE Preamble ........................................................................................................................................

READ Preamble ..........................................................................................................................................

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

4Gb: x4, x8, x16 DDR4 SDRAM

Features

READ Preamble Training ............................................................................................................................ 63

Temperature-Controlled Refresh ................................................................................................................. 63

Command Address Latency ........................................................................................................................ 63

Internal V

REF

Monitor ................................................................................................................................. 63

Maximum Power Savings Mode ................................................................................................................... 64

Mode Register 5 .............................................................................................................................................. 65

Data Bus Inversion ..................................................................................................................................... 66

Data Mask .................................................................................................................................................. 67

CA Parity Persistent Error Mode .................................................................................................................. 67

ODT Input Buffer for Power-Down .............................................................................................................. 67

CA Parity Error Status ................................................................................................................................. 67

CRC Error Status ......................................................................................................................................... 67

CA Parity Latency Mode .............................................................................................................................. 67

Mode Register 6 .............................................................................................................................................. 68

CCD_L Programming ................................................................................................................................. 69

REFDQ

Calibration Enable .......................................................................................................................... 69

REFDQ

Calibration Range ........................................................................................................................... 69

REFDQ

Calibration Value ............................................................................................................................ 70

DQ RX EQ .................................................................................................................................................. 70

Truth Tables ................................................................................................................................................... 71

NOP Command .............................................................................................................................................. 74

DESELECT Command .................................................................................................................................... 74

DLL-Off Mode ................................................................................................................................................ 74

DLL-On/Off Switching Procedures .................................................................................................................. 76

DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 76

DLL-Off to DLL-On Procedure .................................................................................................................... 78

Input Clock Frequency Change ....................................................................................................................... 79

Write Leveling ................................................................................................................................................ 80

DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 81

Procedure Description ................................................................................................................................ 82

Write Leveling Mode Exit ............................................................................................................................ 83

Command Address Latency ............................................................................................................................ 85

Low-Power Auto Self Refresh Mode ................................................................................................................. 90

Manual Self Refresh Mode .......................................................................................................................... 90

Multipurpose Register .................................................................................................................................... 92

MPR Reads ................................................................................................................................................. 93

MPR Readout Format ................................................................................................................................. 95

MPR Readout Serial Format ........................................................................................................................ 95

MPR Readout Parallel Format ..................................................................................................................... 96

MPR Readout Staggered Format .................................................................................................................. 97

MPR READ Waveforms ............................................................................................................................... 98

MPR Writes ............................................................................................................................................... 100

MPR WRITE Waveforms ............................................................................................................................. 101

MPR REFRESH Waveforms ........................................................................................................................ 102

Gear-Down Mode .......................................................................................................................................... 105

Maximum Power-Saving Mode ....................................................................................................................... 108

Maximum Power-Saving Mode Entry .......................................................................................................... 108

Maximum Power-Saving Mode Entry in PDA .............................................................................................. 109

CKE Transition During Maximum Power-Saving Mode ................................................................................ 109

Maximum Power-Saving Mode Exit ............................................................................................................ 109

Command/Address Parity .............................................................................................................................. 111

Per-DRAM Addressability .............................................................................................................................. 119

CCMTD-1725822587-9046

4gb_ddr4_dram.pdf - Rev. K 06/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Recommended Resources

AC and DC inflow automatic switching circuit diagram

Moisture meter circuit diagram

M62213FP some terminal connection circuit diagram a

CD and VCD audio output gating circuit

820e computer motherboard circuit diagram_40

CXA1019S radio circuit

CCS (Code Composer Studio) Tutorial Collection: I recently learned about launchpad in a TI class, and used Code Composer Studio in the process. So I collected some CCS tutorials from the Internet.Share it for everyone to learn...; tiankai001 Microcontroller MCU

Multi-port card IO address/interrupt is specified by BIOS: Where can I find the IO address and interrupt of each serial port of JetCard1404 of CoreHuiTong? I called customer service and they said it is in BIOS, but they don't know where it is. I looked in the...; 天天 Embedded System

Application Notes for the TI430!: ...; 终极菜鸟 Microcontroller MCU

Just a few capacitors in series cost one or two hundred yuan...: ...; clark Discrete Device

Job hunting gift package for fresh graduates: Job hunting gift package for fresh graduates...; 亲善大使 Talking about work

CC3200 camera application problem: [color=rgb(0, 0, 0)]I downloaded the example of websock_camera. You can download it and enter mysiplelink.net/网占. At this time, only Web Camera can be entered, and the others are not found. After ente...; a6784998 Wireless Connectivity

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components