8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Automotive DDR4 SDRAM
MT40A1G8
MT40A512M16
Features
•
•
•
•
•
V
DD
= V
DDQ
= 1.2V ±60mV
V
PP
= 2.5V –125mV/+250mV
On-die, internal, adjustable V
REFDQ
generation
1.2V pseudo open-drain I/O
Refresh time of 8192-cycle at T
C
temperature range:
– 64ms at –40°C to 85°C
– 32ms at 85°C to 95°C
– 16ms at 95°C to 105°C
– 8ms at 105°C to 125°C
16 internal banks (x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register read and write capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
JEDEC JESD-79-4 compliant
sPPR and hPPR capability
AEC-Q100
PPAP submission
Options
1
• Configuration
– 1 Gig x 8
– 512 Meg x 16
• 78-ball FBGA package (Pb-free) – x8
– 8mm x 12mm – Rev. B
7.5mm x 11mm – Rev. E
• 96-ball FBGA package (Pb-free) – x16
– 8mm x 14mm – Rev. B
– 7.5mm x 13.5mm – Rev. E
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.750ns @ CL = 18 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
• Product certification
– Automotive
• Operating temperature
– Industrial (–40° T
C
95°C)
– Automotive (–40° T
C
105°C)
– Ultra-high (–40° T
C
125°C)
3
– Revision
Notes:
Marking
1G8
512M16
WE
SA
JY
LY
-062E
-075E
-083E
A
IT
AT
UT
:B, :E
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
2. The ×4 device is not offered and the mode
is not supported by the x8 or x16 device
even though some ×4 mode descriptions ex-
ist in the datasheet.
3. The UT option use based on automotive us-
age model. Contact Micron sales represen-
tative if you have questions.
4. -062E is only available for die Rev. E.
5. The datasheet is preliminary revision for die
Rev. E.
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. F 01/19 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Table 1: Key Timing Parameters
Speed Grade
1
-062E
-075E
-083E
Note:
Data Rate (MT/s)
3200
2666
2400
Target CL-nRCD-nRP
22-22-22
18-18-18
16-16-16
t
AA
(ns)
t
RCD
(ns)
t
RP
(ns)
13.75
13.5
13.32
13.75
13.5
13.32
13.75
13.5
13.32
1. Refer to the Speed Bin Tables for backward compatibility.
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page size
1
Note:
1024 Meg x 8
4
BG[1:0]
4
BA[1:0]
64K (A[15:0])
1K (A[9:0])
1KB
512 Meg x 16
2
BG0
4
BA[1:0]
64K (A[15:0])
1K (A[9:0])
2KB
1. Page size is per bank, calculated as follows:
Page size = 2
COLBITS
× ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
Figure 1: Order Part Number Example
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. F 01/19 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Contents
Important Notes and Warnings .......................................................................................................................
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
Automotive Temperature ............................................................................................................................
Ultra-high Temperature ..............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Functional Block Diagrams .............................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT R
TT(NOM)
Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
Rx CTLE Control .........................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Hard Post Package Repair Mode ..................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
18
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18
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CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. F 01/19 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
WRITE Preamble ........................................................................................................................................ 58
READ Preamble .......................................................................................................................................... 58
READ Preamble Training ............................................................................................................................ 58
Temperature-Controlled Refresh ................................................................................................................. 58
Command Address Latency ........................................................................................................................ 58
Internal V
REF
Monitor ................................................................................................................................. 58
Maximum Power Savings Mode ................................................................................................................... 59
Mode Register 5 .............................................................................................................................................. 60
Data Bus Inversion ..................................................................................................................................... 61
Data Mask .................................................................................................................................................. 62
CA Parity Persistent Error Mode .................................................................................................................. 62
ODT Input Buffer for Power-Down .............................................................................................................. 62
CA Parity Error Status ................................................................................................................................. 62
CRC Error Status ......................................................................................................................................... 62
CA Parity Latency Mode .............................................................................................................................. 62
Mode Register 6 .............................................................................................................................................. 63
t
CCD_L Programming ................................................................................................................................. 64
V
REFDQ
Calibration Enable .......................................................................................................................... 64
V
REFDQ
Calibration Range ........................................................................................................................... 64
V
REFDQ
Calibration Value ............................................................................................................................ 65
Truth Tables ................................................................................................................................................... 66
NOP Command .............................................................................................................................................. 69
DESELECT Command .................................................................................................................................... 69
DLL-Off Mode ................................................................................................................................................ 69
DLL-On/Off Switching Procedures .................................................................................................................. 71
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 71
DLL-Off to DLL-On Procedure .................................................................................................................... 73
Input Clock Frequency Change ....................................................................................................................... 74
Write Leveling ................................................................................................................................................ 75
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 76
Procedure Description ................................................................................................................................ 77
Write Leveling Mode Exit ............................................................................................................................ 78
Command Address Latency ............................................................................................................................ 80
Low-Power Auto Self Refresh Mode ................................................................................................................. 85
Manual Self Refresh Mode .......................................................................................................................... 85
Multipurpose Register .................................................................................................................................... 87
MPR Reads ................................................................................................................................................. 88
MPR Readout Format ................................................................................................................................. 90
MPR Readout Serial Format ........................................................................................................................ 90
MPR Readout Parallel Format ..................................................................................................................... 91
MPR Readout Staggered Format .................................................................................................................. 92
MPR READ Waveforms ............................................................................................................................... 93
MPR Writes ................................................................................................................................................ 95
MPR WRITE Waveforms .............................................................................................................................. 96
MPR REFRESH Waveforms ......................................................................................................................... 97
Gear-Down Mode .......................................................................................................................................... 100
Maximum Power-Saving Mode ....................................................................................................................... 103
Maximum Power-Saving Mode Entry .......................................................................................................... 103
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 104
CKE Transition During Maximum Power-Saving Mode ................................................................................ 104
Maximum Power-Saving Mode Exit ............................................................................................................ 104
Command/Address Parity .............................................................................................................................. 106
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. F 01/19 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
8Gb: x8, x16 Automotive DDR4 SDRAM
Features
Per-DRAM Addressability .............................................................................................................................. 114
V
REFDQ
Calibration ........................................................................................................................................ 117
V
REFDQ
Range and Levels ........................................................................................................................... 118
V
REFDQ
Step Size ........................................................................................................................................ 118
V
REFDQ
Increment and Decrement Timing .................................................................................................. 119
V
REFDQ
Target Settings ............................................................................................................................... 123
Connectivity Test Mode ................................................................................................................................. 125
Pin Mapping ............................................................................................................................................. 125
Minimum Terms Definition for Logic Equations ......................................................................................... 126
Logic Equations for a ×4 Device .................................................................................................................. 126
Logic Equations for a ×8 Device .................................................................................................................. 127
Logic Equations for a ×16 Device ................................................................................................................ 127
CT Input Timing Requirements .................................................................................................................. 127
Excessive Row Activation ............................................................................................................................... 129
Post Package Repair ....................................................................................................................................... 130
Post Package Repair ................................................................................................................................... 130
Hard Post Package Repair .............................................................................................................................. 131
hPPR Row Repair - Entry ............................................................................................................................ 131
hPPR Row Repair – WRA Initiated (REF Commands Allowed) ...................................................................... 131
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ................................................................. 133
sPPR Row Repair ........................................................................................................................................... 135
hPPR/sPPR Support Identifier ........................................................................................................................ 138
ACTIVATE Command .................................................................................................................................... 138
PRECHARGE Command ................................................................................................................................ 139
REFRESH Command ..................................................................................................................................... 139
Temperature-Controlled Refresh Mode .......................................................................................................... 142
Normal Temperature Mode ........................................................................................................................ 142
Extended Temperature Mode ..................................................................................................................... 142
Fine Granularity Refresh Mode ....................................................................................................................... 145
Mode Register and Command Truth Table .................................................................................................. 145
t
REFI and
t
RFC Parameters ........................................................................................................................ 145
Changing Refresh Rate ............................................................................................................................... 148
Usage with TCR Mode ................................................................................................................................ 148
Self Refresh Entry and Exit ......................................................................................................................... 148
SELF REFRESH Operation .............................................................................................................................. 150
Self Refresh Abort ...................................................................................................................................... 152
Self Refresh Exit with NOP Command ......................................................................................................... 153
Power-Down Mode ........................................................................................................................................ 155
Power-Down Clarifications – Case 1 ........................................................................................................... 160
Power-Down Entry, Exit Timing with CAL ................................................................................................... 161
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 163
CRC Write Data Feature ................................................................................................................................. 165
CRC Write Data ......................................................................................................................................... 165
WRITE CRC DATA Operation ...................................................................................................................... 165
DBI_n and CRC Both Enabled .................................................................................................................... 166
DM_n and CRC Both Enabled .................................................................................................................... 166
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 166
CRC and Write Preamble Restrictions ......................................................................................................... 166
CRC Simultaneous Operation Restrictions .................................................................................................. 166
CRC Polynomial ........................................................................................................................................ 166
CRC Combinatorial Logic Equations .......................................................................................................... 167
Burst Ordering for BL8 ............................................................................................................................... 168
CCMTD-1406124318-10419
8gb_auto_ddr4_dram.pdf - Rev. F 01/19 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2016 Micron Technology, Inc. All rights reserved.
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