MT49H32M9SJ-25:B datasheet, PDF

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MT49H32M9SJ-25:B: DescriptionDynamic random access memory RL dynamic random access memory 288M 32MX9 FBGA; Categorysemiconductor Memory IC Dynamic random access memory; File Size6MB，83 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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MT49H32M9SJ-25:B Overview

Dynamic random access memory RL dynamic random access memory 288M 32MX9 FBGA

MT49H32M9SJ-25:B Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
series	MT49H
Encapsulation	Tray
Factory packaging quantity	1120

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288Mb: x9, x18, x36 CIO RLDRAM 2

Features

CIO RLDRAM 2

MT49H32M9 – 32 Meg x 9 x 8 Banks

MT49H16M18 – 16 Meg x 18 x 8 Banks

MT49H8M36 – 8 Meg x 36 x 8 Banks

Features

• 533 MHz DDR operation (1.067 Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock

frequency)

• Organization

– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36

• 8 internal banks for concurrent operation and maxi-

mum bandwidth

• Reduced cycle time (15ns at 533 MHz)

• Nonmultiplexed addresses (address multiplexing

option available)

• SRAM-type interface

• Programmable READ latency (RL), row cycle time,

and burst sequence length

• Balanced READ and WRITE latencies in order to

optimize data bus utilization

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Differential input data clocks (DKx, DKx#)

• On-die DLL generates CK edge-aligned data and

output data clock signals

• Data valid signal (QVLD)

• 32ms refresh (8K refresh for each bank; 64K refresh

command must be issued in total each 32ms)

• HSTL I/O (1.5V or 1.8V nominal)

• 25–60Ω matched impedance outputs

• 2.5V V

EXT

, 1.8V V

, 1.5V or 1.8V V

DDQ

I/O

• On-die termination (ODT) R

Options

• Clock cycle timing

– 1.875ns @

RC = 15ns

– 2.5ns @

RC = 15ns

– 2.5ns @

RC = 20ns

– 3.3ns @

RC = 20ns

– 5.0ns @

RC = 20ns

• Configuration

– 32 Meg x 9

– 16 Meg x 18

– 8 Meg x 36

• Operating temperature

– Commercial (0° to +95°C)

– Industrial (T

= –40°C to +95°C;

= –40°C to +85°C)

• Package

– 144-ball µBGA

– 144-ball µBGA (Pb-free)

– 144-ball FBGA

– 144-ball FBGA (Pb-free)

• Revision

Note:

Marking

-18

-25E

-25

-33

-5

32M9

16M18

8M36

None

1. Not all options listed can be combined to

define an offered product. Use the part cat-

alog search on micron.com for available of-

ferings.

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x9, x18, x36 CIO RLDRAM 2

Features

Contents

General Description ......................................................................................................................................... 7

Functional Block Diagrams ............................................................................................................................... 8

Ball Assignments and Descriptions ................................................................................................................. 11

Package Dimensions ....................................................................................................................................... 16

Electrical Specifications – I

.......................................................................................................................... 18

Absolute Maximum Ratings ............................................................................................................................ 22

AC and DC Operating Conditions .................................................................................................................... 22

Input Slew Rate Derating ................................................................................................................................ 25

Capacitance ............................................................................................................................................... 28

AC Electrical Characteristics ........................................................................................................................... 29

Temperature and Thermal Impedance ............................................................................................................ 32

Commands .................................................................................................................................................... 34

MODE REGISTER SET (MRS) Command ......................................................................................................... 35

Configuration Tables .................................................................................................................................. 37

Burst Length (BL) ....................................................................................................................................... 37

Address Multiplexing .................................................................................................................................. 39

DLL RESET ................................................................................................................................................. 39

Drive Impedance Matching ........................................................................................................................ 39

On-Die Termination (ODT) ......................................................................................................................... 40

READ Command ............................................................................................................................................ 41

WRITE Command .......................................................................................................................................... 42

AUTO REFRESH (AREF) Command ................................................................................................................. 43

INITIALIZATION Operation ............................................................................................................................ 44

READ Operations ........................................................................................................................................... 47

WRITE Operations .......................................................................................................................................... 53

AUTO REFRESH Operation ............................................................................................................................. 58

On-Die Termination ....................................................................................................................................... 59

Multiplexed Address Mode .............................................................................................................................. 62

Configuration Tables .................................................................................................................................. 66

REFRESH Command in Multiplexed Address Mode ..................................................................................... 66

IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 71

Disabling the JTAG Feature ......................................................................................................................... 71

Test Access Port (TAP) ..................................................................................................................................... 71

Test Clock (TCK) ......................................................................................................................................... 71

Test Mode Select (TMS) .............................................................................................................................. 71

Test Data-In (TDI) ...................................................................................................................................... 72

Test Data-Out (TDO) .................................................................................................................................. 72

TAP Controller ................................................................................................................................................ 73

Test-Logic-Reset ......................................................................................................................................... 73

Run-Test/Idle ............................................................................................................................................. 73

Select-DR-Scan .......................................................................................................................................... 73

Capture-DR ................................................................................................................................................ 73

Shift-DR ..................................................................................................................................................... 73

Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 73

Update-DR ................................................................................................................................................. 73

Instruction Register States .......................................................................................................................... 73

TAP Reset ....................................................................................................................................................... 74

TAP Registers ................................................................................................................................................. 75

Instruction Register .................................................................................................................................... 75

Bypass Register .......................................................................................................................................... 75

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

288Mb: x9, x18, x36 CIO RLDRAM 2

Features

List of Figures

Figure 1: 288Mb RLDRAM 2 CIO Part Numbers ................................................................................................ 2

Figure 2: State Diagram ................................................................................................................................... 7

Figure 3: 32 Meg x 9 Functional Block Diagram ................................................................................................. 8

Figure 4: 16 Meg x 18 Functional Block Diagram ............................................................................................... 9

Figure 5: 8 Meg x 36 Functional Block Diagram ............................................................................................... 10

Figure 6: 144-Ball µBGA ................................................................................................................................. 16

Figure 7: 144-Ball FBGA ................................................................................................................................. 17

Figure 8: Minimum Slew Rate ........................................................................................................................ 23

Figure 9: Clock Input ..................................................................................................................................... 24

Figure 10: Nominal

AS/

CS/

DS and

AH/

CH/

DH Slew Rate .......................................................................... 28

Figure 11: AC Outputs – Equivalent Load ........................................................................................................ 31

Figure 12: Example Temperature Test Point Location ...................................................................................... 33

Figure 13: Mode Register Set .......................................................................................................................... 35

Figure 14: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 36

Figure 15: Read Burst Lengths ........................................................................................................................ 38

Figure 16: On-Die Termination-Equivalent Circuit .......................................................................................... 40

Figure 17: READ Command ........................................................................................................................... 41

Figure 18: WRITE Command ......................................................................................................................... 42

Figure 19: AUTO REFRESH Command ........................................................................................................... 43

Figure 20: Power-Up/Initialization Sequence ................................................................................................. 45

Figure 21: Power-Up/Initialization Flow Chart ................................................................................................ 46

Figure 22: Basic READ Burst Timing ............................................................................................................... 47

Figure 23: Consecutive READ Bursts (BL = 2) .................................................................................................. 48

Figure 24: Consecutive READ Bursts (BL = 4) .................................................................................................. 49

Figure 25: READ-to-WRITE ............................................................................................................................ 49

Figure 26: Read Data Valid Window for x9 Device ........................................................................................... 50

Figure 27: Read Data Valid Window for x18 Device .......................................................................................... 51

Figure 28: Read Data Valid Window for x36 Device .......................................................................................... 52

Figure 29: WRITE Burst ................................................................................................................................. 53

Figure 30: Consecutive WRITE-to-WRITE ....................................................................................................... 54

Figure 31: WRITE-to-READ ............................................................................................................................ 55

Figure 32: WRITE-to-READ – Separated by Two NOP Commands .................................................................... 56

Figure 33: WRITE – DM Operation ................................................................................................................. 57

Figure 34: AUTO REFRESH Cycle ................................................................................................................... 58

Figure 35: READ Burst with ODT .................................................................................................................... 59

Figure 36: READ-NOP-READ with ODT .......................................................................................................... 60

Figure 37: READ-to-WRITE with ODT ............................................................................................................ 61

Figure 38: Command Description in Multiplexed Address Mode ..................................................................... 62

Figure 39: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 63

Figure 40: Mode Register Definition in Multiplexed Address Mode .................................................................. 64

Figure 41: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 66

Figure 42: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 67

Figure 43: WRITE-to-READ with Multiplexed Addressing ................................................................................ 68

Figure 44: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 69

Figure 45: READ-to-WRITE with Multiplexed Addressing ................................................................................ 70

Figure 46: TAP Controller State Diagram ......................................................................................................... 74

Figure 47: TAP Controller Block Diagram ........................................................................................................ 74

Figure 48: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 78

Figure 49: TAP Timing ................................................................................................................................... 78

PDF: 09005aef80a41b46

rldram-2_cio_288mb.pdf - Rev. Q 10/15 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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