EDBA164B2PR-1D-F-R datasheet, PDF

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EDBA164B2PR-1D-F-R: DescriptionDynamic Random Access Memory LPDDR2 16G 256MX64 FBGA QDP; Categorysemiconductor Memory IC Dynamic random access memory; File Size2MB，153 Pages; ManufacturerMicron; Websitehttp://www.micron.com/; Environmental Compliance

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EDBA164B2PR-1D-F-R Overview

Dynamic Random Access Memory LPDDR2 16G 256MX64 FBGA QDP

EDBA164B2PR-1D-F-R Parametric

Parameter Name	Attribute value
Maker	Micron
Product Category	dynamic random access memory
type	SDRAM Mobile - LPDDR2
Data bus width	64 bit
organize	256 M x 64
Package/box	FBGA-216
storage	16 Gbit
maximum clock frequency	533 MHz
interview time	5.5 ns
Supply voltage - max.	1.95 V
Supply voltage - min.	1.14 V
Supply current—max.	100 mA
Minimum operating temperature	- 30 C
Maximum operating temperature	+ 85 C
series	EDB
Encapsulation	Cut Tape
Encapsulation	MouseReel
Encapsulation	Reel
Installation style	SMD/SMT
Factory packaging quantity	1000

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216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

LPDDR2 SDRAM

EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR

Features

• Ultra-low-voltage core and I/O power supplies

• Frequency range

– 533 MHz (data rate: 1066 Mb/s/pin)

• 4n prefetch DDR architecture

• 8 internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_c

edge

• Bidirectional/differential data strobe per byte of

data (DQS_t/DQS_c)

• Programmable READ and WRITE latencies (RL/WL)

• Burst length: 4, 8, and 16

• Per-bank refresh for concurrent operation

• Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock-stop capability

• Lead-free (RoHS-compliant) and halogen-free

packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate Data Rate

(MHz)

(Mb/s/pin)

533

1066

Options

• Density/Page Size

– 8Gb/2-CS – dual die

– 16Gb/4-CS – quad die

• Organization

– x64

• V

DD1

DD2

DDQ

: 1.8V/1.2V/1.2V

• Revision

– Dual die

– Quad die

• FBGA “green” package

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

– 12mm x 12mm x 0.8mm, 216-ball

PoP FBGA package, dual die

– 12mm x 12mm x 1.0mm, 216-ball

PoP FBGA package, quad die

– 14mm x 14mm x 0.7mm, 220-ball

PoP FBGA package, dual die

• Timing – cycle time

– 1.875ns @ RL = 8

• Special options

– Non-Automotive

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +85°C

– From –40°C to +105°C

Marking

-1D

blank

Table 2: S4 Configuration Addressing

Architecture

Die configuration

Row addressing

Column addressing

Number of die

Die per rank

Ranks per channel

Note:

128 Meg x 64

16 Meg x 32 x 8 banks x 2 channel

16K A[13:0]

1K A[9:0]

256 Meg x 64

32 Meg x 32 x 8 banks x 2 channel

16K A[13:0]

1K A[9:0]

1. A channel is a complete LPDRAM interface, including command/address and data pins.

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

Contents

LPDDR2 Array Configuration ............................................................................................................................ 9

General Notes .............................................................................................................................................. 9

Specifications ........................................................................................................................................... 10

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 18

Ball Assignments ............................................................................................................................................ 21

Ball Descriptions ............................................................................................................................................ 24

Functional Description ................................................................................................................................... 25

Simplified State Diagram ................................................................................................................................ 26

Power-Up and Initialization ............................................................................................................................ 28

Voltage Ramp and Device Initialization ....................................................................................................... 28

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 30

Power-Off Sequence ....................................................................................................................................... 30

Uncontrolled Power-Off Sequence .............................................................................................................. 31

Mode Register Definition ................................................................................................................................ 31

Mode Register Assignments and Definitions ................................................................................................ 31

Commands and Timing .................................................................................................................................. 42

ACTIVATE Command ..................................................................................................................................... 43

8-Bank Device Operation ............................................................................................................................ 44

Read and Write Access Modes ......................................................................................................................... 45

Burst READ Command ................................................................................................................................... 45

READs Interrupted by a READ ..................................................................................................................... 52

Burst WRITE Command .................................................................................................................................. 52

WRITEs Interrupted by a WRITE ................................................................................................................. 55

BURST TERMINATE Command ...................................................................................................................... 55

Write Data Mask ............................................................................................................................................. 57

PRECHARGE Command ................................................................................................................................. 58

READ Burst Followed by PRECHARGE ......................................................................................................... 59

WRITE Burst Followed by PRECHARGE ....................................................................................................... 60

Auto Precharge operation ........................................................................................................................... 61

READ Burst with Auto Precharge ................................................................................................................. 61

WRITE Burst with Auto Precharge ............................................................................................................... 62

REFRESH Command ...................................................................................................................................... 64

REFRESH Requirements ............................................................................................................................. 66

SELF REFRESH Operation ............................................................................................................................... 73

Partial-Array Self Refresh – Bank Masking .................................................................................................... 75

Partial-Array Self Refresh – Segment Masking .............................................................................................. 75

MODE REGISTER READ ................................................................................................................................. 76

Temperature Sensor ................................................................................................................................... 78

DQ Calibration ........................................................................................................................................... 80

MODE REGISTER WRITE Command ............................................................................................................... 82

MRW RESET Command .............................................................................................................................. 82

MRW ZQ Calibration Commands ................................................................................................................ 83

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 85

Power-Down .................................................................................................................................................. 85

Deep Power-Down ......................................................................................................................................... 92

Input Clock Frequency Changes and Stop Events ............................................................................................. 93

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 93

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 94

NO OPERATION Command ............................................................................................................................ 94

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

Truth Tables ................................................................................................................................................... 94

Absolute Maximum Ratings ........................................................................................................................... 102

Input/Output Capacitance ............................................................................................................................. 102

Electrical Specifications – I

Specifications and Conditions ........................................................................... 103

AC and DC Operating Conditions ................................................................................................................... 106

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 107

REF

Tolerances ......................................................................................................................................... 108

Input Signal .............................................................................................................................................. 110

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 112

Single-Ended Requirements for Differential Signals .................................................................................... 113

Differential Input Crosspoint Voltage ......................................................................................................... 115

Input Slew Rate ......................................................................................................................................... 116

Output Characteristics and Operating Conditions ........................................................................................... 116

Single-Ended Output Slew Rate .................................................................................................................. 117

Differential Output Slew Rate ..................................................................................................................... 118

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 120

Output Driver Impedance .............................................................................................................................. 121

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 122

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 123

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 123

Clock Specification ........................................................................................................................................ 126

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 128

Clock Period Jitter .......................................................................................................................................... 128

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 128

Cycle Time Derating for Core Timing Parameters ........................................................................................ 129

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 129

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 129

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 129

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 130

Refresh Requirements Parameters .................................................................................................................. 131

AC Timing ..................................................................................................................................................... 131

CA and CS_n Setup, Hold, and Derating .......................................................................................................... 137

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 145

Revision History ............................................................................................................................................ 152

Rev. F – 08/16 ............................................................................................................................................ 152

Rev. E – 05/16 ............................................................................................................................................ 152

Rev. D – 03/16 ............................................................................................................................................ 152

Rev. C – 02/16 ............................................................................................................................................ 152

Rev. B – 01/15 ............................................................................................................................................ 152

Rev. A – 09/14 ............................................................................................................................................ 152

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Features

List of Figures

Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2

Figure 2: Dual Die Single Rank, Dual Channel Package Block Diagram ............................................................. 16

Figure 3: Quad Die Dual Rank, Dual Channel Package Block Diagram ............................................................. 17

Figure 4: 216-Ball FBGA (12mm x 12mm x 0.8mm) – EDB8164B4PR, EDB8164B4PT ......................................... 18

Figure 5: 216-Ball FBGA (12mm x 12mm x 1.0mm) – EDBA164B2PR ................................................................ 19

Figure 6: 220-Ball FBGA (14mm x 14mm x 0.7mm) – EDB8164B4PK ................................................................ 20

Figure 7: 216-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 21

Figure 8: 220-Ball Dual-Channel FBGA – 2 x 4Gb Die ...................................................................................... 22

Figure 9: 216-Ball Dual-Channel FBGA – 4 x 4Gb Die ...................................................................................... 23

Figure 10: Functional Block Diagram ............................................................................................................. 26

Figure 11: Simplified State Diagram ............................................................................................................... 27

Figure 12: Voltage Ramp and Initialization Sequence ...................................................................................... 30

Figure 13: Command and Input Setup and Hold ............................................................................................. 43

Figure 14: CKE Input Setup and Hold ............................................................................................................. 43

Figure 15: ACTIVATE Command .................................................................................................................... 44

Figure 16:

FAW Timing (8-Bank Devices) ....................................................................................................... 45

Figure 17: READ Output Timing –

DQSCK (MAX) ........................................................................................... 46

Figure 18: READ Output Timing –

DQSCK (MIN) ........................................................................................... 46

Figure 19: Burst READ – RL = 5, BL = 4,

DQSCK >

CK ..................................................................................... 47

Figure 20: Burst READ – RL = 3, BL = 8,

DQSCK <

CK ..................................................................................... 47

Figure 21:

DQSCKDL Timing ........................................................................................................................ 48

Figure 22:

DQSCKDM Timing ....................................................................................................................... 49

Figure 23:

DQSCKDS Timing ......................................................................................................................... 50

Figure 24: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 51

Figure 25: Seamless Burst READ – RL = 3, BL = 4,

CCD = 2 .............................................................................. 51

Figure 26: READ Burst Interrupt Example – RL = 3, BL = 8,

CCD = 2 ................................................................. 52

Figure 27: Data Input (WRITE) Timing ........................................................................................................... 53

Figure 28: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 53

Figure 29: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 54

Figure 30: Seamless Burst WRITE – WL = 1, BL = 4,

CCD = 2 ............................................................................ 54

Figure 31: WRITE Burst Interrupt Timing – WL = 1, BL = 8,

CCD = 2 ................................................................ 55

Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 56

Figure 33: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 57

Figure 34: Data Mask Timing ......................................................................................................................... 57

Figure 35: Write Data Mask – Second Data Bit Masked .................................................................................... 58

Figure 36: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(

RTP(MIN)/

CK) = 2 ................................ 59

Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 3 ................................ 60

Figure 38: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 61

Figure 39: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 2 ........................................ 62

Figure 40: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 63

Figure 41:

SRF Definition .............................................................................................................................. 67

Figure 42: Regular Distributed Refresh Pattern ............................................................................................... 69

Figure 43: Supported Transition from Repetitive REFRESH Burst .................................................................... 70

Figure 44: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 71

Figure 45: Recommended Self Refresh Entry and Exit ..................................................................................... 72

Figure 46: All-Bank REFRESH Operation ........................................................................................................ 73

Figure 47: Per-Bank REFRESH Operation ....................................................................................................... 73

Figure 48: SELF REFRESH Operation .............................................................................................................. 74

Figure 49: MRR Timing – RL = 3,

MRR = 2 ...................................................................................................... 76

Figure 50: READ to MRR Timing – RL = 3,

MRR = 2 ......................................................................................... 77

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDBA164B2PR-1D-F-R Related Products

	EDBA164B2PR-1D-F-R	EDB8164B4PT-1DIT-F-R	EDB8164B4PR-1D-F-R	EDB8164B4PT-1D-F-R	EDB8164B4PK-1D-F-R
Description	Dynamic Random Access Memory LPDDR2 16G 256MX64 FBGA QDP	Dynamic Random Access Memory LPDDR2 8G 128MX64 FBGA DDP	Dynamic Random Access Memory LPDDR2 8G 128MX64 FBGA DDP	Dynamic Random Access Memory LPDDR2 8G 128MX64 FBGA DDP	Dynamic Random Access Memory LPDDR2 8G 128MX64 FBGA DDP
Maker	Micron	Micron	Micron	Micron	Micron
Product Category	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory	dynamic random access memory
type	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2	SDRAM Mobile - LPDDR2
Data bus width	64 bit	64 bit	64 bit	64 bit	64 bit
organize	256 M x 64	128 M x 64	128 M x 64	128 M x 64	128 M x 64
Package/box	FBGA-216	FBGA-216	FBGA-216	FBGA-216	FBGA-220
storage	16 Gbit	8 Gbit	8 Gbit	8 Gbit	8 Gbit
maximum clock frequency	533 MHz	533 MHz	533 MHz	533 MHz	533 MHz
interview time	5.5 ns	5.5 ns	5.5 ns	5.5 ns	5.5 ns
Supply voltage - max.	1.95 V	1.95 V	1.95 V	1.95 V	1.95 V
Supply voltage - min.	1.14 V	1.14 V	1.14 V	1.14 V	1.14 V
Supply current—max.	100 mA	100 mA	100 mA	100 mA	100 mA
Minimum operating temperature	- 30 C	- 40 C	- 30 C	- 30 C	- 30 C
Maximum operating temperature	+ 85 C	+ 85 C	+ 85 C	+ 85 C	+ 85 C
series	EDB	EDB	EDB	EDB	EDB
Installation style	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT	SMD/SMT
Factory packaging quantity	1000	1000	1000	1000	1000
Encapsulation	Reel	Reel	Reel	Reel	Reel

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