DEMO CIRCUIT 1 0 6 3
Q UICK S TA RT
LT6559
G UIDE
L T6 5 5 9
Trip le 3 0 0 MH z V id e o Op e ra tio n a l A m p lifie r
DESCRIPTION
Demonstration circuit 1063 f
eatures the LT6559 Tripl
e
300M Hz Video Operational Ampl ier. The LT6559 is
if
designed f RGB video cabl
or
e-driver appl
ications
operating f
rom a singl 5V suppl As show n in Figure 1,
e
y.
the f
orm-f
actor of this demo circuit alow s a PC video
l
port to serve as a high-speed signalsource. Rapid video
eval
uation can be perf
ormed by simpl inserting the
y
board in-l w ith the RGB monitor cabl and connecting
ine
e
a 5V pow er source to it.
Device characteristics that are demonstrated in the
ormance Summary bel .
ow
DC1063 are show n in the Perf
Figure 1. LT6559 on D C1063, Show n Act Size
ual
Design f es f t circuit board are avail e. Cal
il or his
abl
l
t LTC f ory.
he
act
,LT,are registered trademarks ofLinear Technol Corporation. Other product names
ogy
may be trademarks ofthe companies that manuf
acture the products.
PERF ORM A NCE SU M M A RY
Specif ions are atT
A
= 25°C
icat
SYM BOL
V+
Z
IN
Z
OUT
A
BW
SR
V
IN
I
S
PARAM ETER
Input Suppl Range
y
Input Impedance
Output Impedance
Gain
Bandw idth
Sl Rate
ew
Input signalsw ing
Pow er Suppl Current
y
CONDI ONS
TI
1.4VP-P ampl ier output sw ing
if
MI
N
4.75
ac-coupl
ed
ac-coupl
ed
Output terminated into 75Ω
Output terminated into hi-Z
-3dB,smal-signal
l
V+= 5V
V+= 5V,no output cl
ipping
V+= 5V,no signal
TYP
5
75
75
0
+6
300
600
15
M AX
12
1.3
UNI
TS
V
Ω
Ω
dB
dB
M Hz
V/
µs
V
P-P
mA
OPERA TING PRINCIPL ES
DC1063 simpl inserts LT6559 ampl ier stages in series
y
if
w ith the Red,Green,and Bl video signal ofa standard
ue
s
High-Density 15-contact D-subminature PC monitor
connection (“VGA” port). Al other standard connections
l
are passed-through to alow normal monitor operation,
l
as show n in the schematic diagram in Figure 5.
The ampl ier sections terminate the incoming signalinto
if
75Ω, then ac-coupl to the non-inverting input of each
e
ampl ier w ith a 22µF capacitor. DC biasing of the
if
ac-coupl signal is provided by resistor dividers that
ed
s
nominaly divide the suppl vol
l
y tage in hal. Gain of each
f
section is set to tw o by equal ue f
-val eedback resistors
(ac-coupl so that dc gain is unity f biasing
ed
or
1
LT6559
purposes). The sel
ection of f
eedback resistor val is
ue
important to optimize the f
requency response, since the
LT6559 is a current-f
eedback topol
ogy op-amp. The
ampl ier outputs are then back-terminated in 75Ω and
if
ac-coupl via 220µF capacitors to the video cabl
ed
e
connection. The back-terminations inherentl f
y orm a 2:
1
vol
tage division at the destination l
oads, theref the
ore
overal video insertion gain of the DC1063 is unity. This
l
means that pl
acing the DC1063 in-l w ith the normal
ine
monitor connection w il resul in onl introducing
l
t
y
artif
acts associated w ith f
requency response and l
inearity
of the LT6559. For displ f
ay ormats w ith about 7ns or
l
onger
pixel
times
(“SXGA”
resol
utions,
1280x1024@ 75Hz f instance), no visual dif erentiation
or
f
is normaly discernabl verif
l
e,
ying the suitabil of the
ity
LT6559 f use in the actual appl
or
ication (note: a
“phasing” tw eak may be required w ith LCD displ to
ays
or
ay
if
account f about 2ns del through the video ampl iers
vs. no del f the syncs). Figure 2 show s the w el-
ay or
l
behaved time response of the LT6559 on DC1063
passing a nominal 7.5ns/
700mV
P-P
video pul (the
se
50Ω
displ ampl
ay
itude is scal 42.3% due to a 75Ω/
ed
min-l conversion adapter, thus nominaly 296mV
P-P
oss
l
at the instrument; note the actual vol
tage sw ing at the
op-amp output is 1.4V
P-P
).
In PC appl
ications, l the DC1063 is designed to
ike
highl
ight, the RGB video sw ings are 700mV
P-P
. For ac-
coupl
ing as used on the DC1063, varying picture
conditions can expand the dynamic operational range to
approximatel 1.2V
P-P
at the input. Even this expanded
y
range is readil handl by the LT6559 on a singl 5V
y
ed
e
pow er suppl
y.
An ENabl j
e umper is provided, that w hen removed (or
rel
ocated to the al
ternate pin-pair) disabl the LT6559
es
w hil pow er remains appl
e
ied. The j
umper does not
disconnect the input biasing resistors how ever,so at 5V,
about 2.3mA of residual resistor current w il fow in the
ll
shutdow n condition that is not attributabl to the LT6559
e
itsel.
f
Figure 2. LT6559 Large-SignalPul R esponse in D C1063
se
Q U ICK STA RT PROCEDU RE
Demonstration circuit 1063 is easy to set up to eval
uate
the perf
ormance of the LT6559. Ref to Figure 3 f
er
or
proper measurement equipment setup and f l the
olow
procedure bel :
ow
NOTE.
Due to the Ul High Frequencies (UHF) invol RF measurement
tra
ved,
practices are required to accuratel instrument the perf
y
ormance ofthe
LT6559.
2.
W hil disconnected f
e
rom the DC1063, set a pow er
suppl to 5V (or other vol
y
tage up to 12V, if desired),
then de-energize.
3.
Instal DC1063 into PC monitor port. J1, the l t-side
l
ef
connector (w ith pins) is the side to connect to the PC.
A “VGA” extender cabl may be used if circumstances
e
don’ permit convenient instalation ofDC1063 directl
t
l
y
to the PC (note that such a cabl may induce subtl
e
e
settl anomal in an osciloscope presentation that
ing
ies
l
are unrel
ated to the perf
ormance ofthe LT6559).
1.
Pl verif j
ace/ y umper in the f l ing position:
olow
e
JP1
ENabl position
2
LT6559
4.
Attach the pow er cl eads according to the sil
ip-l
k-
screened l
egends. Suppl ground is tied to the turret
y
cl
osest to J1. Suppl pow er (+5V normaly) is tied to
y
l
the turret nearest the ENabl j
e umper. Use caution to
avoid shorting cl together or to other points of the
ips
circuitry.
5.
Connect the video monitor cabl to J2. J2 is the right-
e
side connector (w ith receptacl
es). The video cabl
e
may drive a video displ or other instrumentation as
ay
desired in the eval
uation.
6.
Pow er up the DC1063 pow er source. A normal video
presentation shoul be seen on a video monitor, or a
d
specif signalat the test equipment being used. If an
ic
LCD video displ is being used,re-tuning of the sync
ay
“phasing” may be required to optimize the internal
w avef
orm sampl times due to about 2ns sync shif
ing
t
through DC1063 (ref to the LCD displ Operators’
er
ay
M anualf detail For instrumentation hookup, keep
or
s).
cabl l
e engths as short as practicabl W hen 75Ω test
e.
equipment is not avail e, use qual 75Ω to 50Ω
abl
ity
adapters (w ideband “min-l
oss pads”) and 50Ω
instrument settings f best resul
or
ts.
Computer Monitor
PC
(Rear Panel)
Power Supply
COM +
Figure 3. Proper M easurem entEquipm entSet
up
I
TEM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QTY
6
3
1
1
2
1
1
1
1
3
6
6
3
1
REFERENCE
C1-C6
C7-C9
C10
C11
E1,
E2
J1
J2
JP1
SH1
R1-R3
R4-R9
R10-R15
R16-R18
U1
PART DESCRI ON
PTI
CAP.,X5R,22uF,6.3V,20% ,
1206
CAP.,POSCAP,220uF,6.3V,2816
CAP.,X7R,0.1uF, 5% ,
16V, 0603
CAP.,X5R,4.7uF, 20% ,
16V,
1206
TESTPOINT,TURRET,0.064
CONN,
HD-15, ALE,
M
HORZ-PCB
CONN,
HD-15, ALE,
FEM
HORZ-PCB
0.079 SINGLE ROW HEADER,3 PIN
SHUNT,
RES.,
CHIP,78.7,1% ,0402
RES.,
CHIP,3.32K, 1% ,0402
RES.,
CHIP,301,1% ,0402
RES.,
CHIP,75,1% ,
0402
IC.,LT6559CUD,QFN16
M ANUFACTURER /PART #
AVX,12066D226M AT
SANYO,6TPE220M I
AVX,0603YC104JAT
Taiyo Yuden EM K316BJ475M L-T
M ILL-M AX 2308-2
AM P 5749767-1
AM P 1-1470250-3
SAM TEC,TM M 103-02-L-S
SAM TEC,2SN-BK-G
VISHAY,CRCW 040278R7FKED
VISHAY,CRCW 04023K32FKED
VISHAY,CRCW 0402301RFKED
VISHAY,CRCW 040275R0FKED
LINEAR TECH.,LT6559CUD
Figure 4. Bil ofM at
l
erial(BO M ) f D C1063
or
3
LT6559
Figure 5. D C1063 El ricalSchem at Diagram
ect
ic
4
Mouser Electronics
Authorized Distributor
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:
DC1063A
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