AS4C32M32MD2A-25BIN
AS4C64M16MD2A-25BIN
Revision History
1G (64M x 16
and 32M x 32)
Low Power
DDR2 SDRAM
134ball
FBGA Package
AS4C64M16MD2A-25BIN/AS4C32M32MD2A-25BIN
Revision
Rev 1.0
Details
Preliminary datasheet
Date
Jan
2018
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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AS4C32M32MD2A-25BIN
AS4C64M16MD2A-25BIN
DDR Sync DRAM Features
•
Functionality
-
VDD2 = 1.14–1.30V
-
VDDCA/VDDQ = 1.14–1.30V
-
VDD1 = 1.70–1.95V
- Interface : HSUL_12
- Data width : x16 / x32
- Clock frequency range : 400 MHz
- Four-bit pre-fetch DDR architecture
- Eight internal banks for concurrent operation
- Multiplexed, double data rate, command/address inputs;
commands entered on every CK edge
- Bidirectional/differential data strobe per byte of
data(DQS/DQS#).
-
DM masks write date at the both rising and falling edge of
the data strobe
- Programmable READ and WRITE latencies (RL/WL)
- Programmable burst lengths: 4, 8, or 16
-
Auto refresh and self refresh supported
-
All bank auto refresh and per bank auto refresh supported
- Clock stop capability
•
Configuration
- 64 Meg X
16 (8 Meg X 16 X 8 Banks).
- 32 Meg X
32 (4 Meg X 32 X 8 Banks).
•
Low Power Features
- Low voltage power supply.
- Auto TCSR (Temperature Compensated Self
Refresh).
- PASR (Partial Array Self Refresh) power-saving mode.
- DPD (Deep Power Down) Mode.
- DS (Driver Strength) Control.
•
Timing – Cycle Time
-
2.5ns
-
3.0ns
@ RL = 6
@ RL = 5
(-40℃ to +85℃).
•
Operating Temperature Ranges
- Industrial
•
Package
- 134-Ball FBGA(10.0mm x 11.5mm x 1.0mm)
Table 1. Ordering Information
Product Part No.
AS4C64M16MD2A-25BIN
AS4C32M32MD2A-25BIN
Org.
64M x 16
32M x 32
Temperature
-40°C to 85°C
-40°C to 85°C
Max Clock (MHz)
400
400
Package
134-ball FBGA
134-ball FBGA
Table 2. Speed Grade Information
Speed Grade
DDR2L-800
Clock Frequency
400
MHz
RL
6
WL
3
t
RCD
(ns)
18
t
RP
(ns)
18
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AS4C32M32MD2A-25BIN
AS4C64M16MD2A-25BIN
Logic Block Diagram
CK #
CK
CKE
CS#
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
Row Address
R Latch & decoders
R Latch & decoders
RLatch & decoders
R Latch & decoders
R Latch & decoders
RLatch & decoders
RLatch & decoders
Latch & decoders
Control
Logic
Bank7
Bank6
Bank5
Bank4
Bank3
Bank2
Bank1
Bank0
Memory
Array
DQS
Generator
Sense amp
Confidential
Command / Address
Multiplex and
Decode
Mode
Registe
r
4n
Read
Latch
Mux
n
DATA
DRVRS
DQ0 – DQn-1
x
Refresh
Counter
Row
Address
Mux
x
DQS , /DQS
3
3
Bank
Control
Logic
I/O gating
DM mask logic
4n
4n
Write
FIFO
And
Drivers
8
Mask
Bank
Control
Logic
4n
`
Column Decoder
CK, CK# CK out
CK in
`
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
RCVRS
DQS , DQS#
DM
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AS4C32M32MD2A-25BIN
AS4C64M16MD2A-25BIN
General Description
The
1Gb
Mobile Low-Power DDR2 SDRAM (LPDDR2) is a high-speed CMOS, dynamic random-access memory containing
1,073,741,824 bits. The LPDDR2-S4 device is internally configured as an eight-bank DRAM. Each of the x16’s 134,217,728
-bit banks is organized as 8,192 rows by 1024 columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as
8,192 rows by 512 columns by 32 bits.
Simplified Bus Interface State Diagram
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AS4C32M32MD2A-25BIN
AS4C64M16MD2A-25BIN
Address Table
Parameter
Configuration
Bank Address
Row Address
Column Address
64Mb X 16
8Mb x 8banks x 16
BA0 ~ BA2
R0 ~ R12
C0 ~ C9
32Mb X 32
4Mb x 8banks x 32
BA0 ~ BA2
R0 ~ R12
C0 ~ C8
Note : 1. The least-significant column address CA0 is not transmitted on the CA bus, and is implied to be zero.
Pin Description(X16)
Symbol
CK, CK#
Type
Input
Description
Clock :
CK and CK# are differential clock inputs.
All CA inputs are sampled on both rising and falling edges of CK. CS and CKE inputs
are sampled at the rising edge of CK. AC timings are referenced to clock.
Clock enable :
CKE HIGH activates and CKE LOW deactivates the internal clock
signals, input buffers, and output drivers. Power-saving modes are entered and exited
via CKE transitions. CKE is considered part of the command code. CKE is sampled at
the rising edge of CK.
Chip select :
CS# is considered part of the command code and is sampled at the
rising edge of CK.
Input data mask :
DM is an input mask signal for WRITE data. Although DM balls
are input-only, the DM loading is designed to match that of DQ and DQS balls.
DM[1:0] is DM for each of the two data bytes, respectively.
Data input/output :
Bidirectional data bus.
Data strobe :
The data strobe is bidirectional (used for read and write data) and com-
plementary (DQS and DQS#). It is edge-aligned output with read data and centered
input with write data. DQS[1:0]/DQS[1:0]# is DQS for each of the two data bytes, res-
pectively.
Command/address inputs:
Provide the command and address inputs according to
the command truth table.
DQ Power
: Provide isolated power to DQs for improved noise immunity.
DQ Ground
: Provide isolated ground to DQs for improved noise immunity.
Command/address power supply :
Command/address power supply.
Command/address ground :
Isolated on the die for improved noise immunity.
Core power :
Supply 1.
Core power :
Supply 2.
Common ground
Reference voltage :
VREFCA is reference for command/address input buffers,
VREFDQ is reference for DQ input buffers.
External impedance (240 ohm) :
This signal is used to calibrate the device output
impedance for S4 devices. For S2 devices, ZQ should be tied to VDDCA.
Do not use :
Must be grounded or left floating.
No connect :
Not internally connected.
No connect :
Balls indicated as (NC) are no connects, however, they could be
connected together internally.
CKE
Input
CS#
Input
DM0–DM1
DQ0 – DQ15
DQS0 – DQS1
DQS0# – DQS1#
Input
Input
I/O
CA0 – CA9
VDDQ
VSSQ
VDDCA
VSSCA
VDD1
VDD2
VSS
VREFCA,
VREFDQ
ZQ
DNU
NC
(NC)
Input
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Reference
–
–
–
Confidential
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Rev.1.0
Jan. 2018
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